📄 jtag_control.vhd
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end if;
end if;
execute_2 := execute_1;
execute_1 := execute;
end if;
end process Execute_FIFO_Command;
Debug_SYS_Rst <= Debug_SYS_Rst_i;
Debug_Rst <= Debug_Rst_i;
Ext_NM_BRK <= Ext_NM_BRK_i;
Ext_BRK_FDRSE : FDRSE
port map (
Q => ext_BRK_i, -- [out std_logic]
C => OPB_Clk, -- [in std_logic]
CE => '0', -- [in std_logic]
D => '0', -- [in std_logic]
R => Clear_Ext_BRK, -- [in std_logic]
S => set_Ext_BRK); -- [in std_logic]
Ext_BRK <= ext_BRK_i;
Dbg_Clk <= DRCK;
-----------------------------------------------------------------------------
-- Handling the Which_MB register
-----------------------------------------------------------------------------
More_Than_One: if (C_MB_DBG_PORTS > 1) generate
signal Which_MB_Reg_En : std_logic;
signal Which_MB_Reg : std_logic_vector(0 to 7);
begin
Which_MB_Reg_En <= '1' when Dbg_Reg_En_I(0 to 4) = MDM_WRITE_WHICH_MB else '0';
Which_MB_Reg_Handle : process (DRCK) is
variable temp : std_logic_vector(Which_MB_Reg'range) := (others => '0');
begin -- process Which_MB_Reg_Handle
if DRCK'event and DRCK = '1' then -- rising clock edge
if Which_MB_Reg_En = '1' and shifting_Data = '1' then
temp(0 to temp'right-1) := temp(1 to temp'right);
temp(temp'right) := tdi_reg;
if (Dbg_Update_I = '1') then
Which_MB_Reg <= temp(Which_MB_Reg'range);
end if;
end if;
end if;
end process Which_MB_Reg_Handle;
MB_Debug_Enabled(0 to C_MB_DBG_PORTS-1) <= Which_MB_Reg(0 to C_MB_DBG_PORTS-1);
-- -- Create the enables for each MicroBlaze debug port
-- Create_MB_Dbg_Port_Enables: process (Which_MB_Reg) is
-- constant max_no_bits : natural := log2(C_MB_DBG_PORTS);
-- variable bits_to_use : std_logic_vector(0 to max_no_bits-1);
-- begin -- process Create_MB_Dbg_Port_Enables
-- MB_Debug_Enabled <= (others => '0'); -- Default
-- if (Which_MB_Reg = "11111111") then
-- MB_Debug_Enabled <= (others => '1'); -- Broadcast command
-- else
-- bits_to_use := Which_MB_Reg(bits_to_use'range);
-- for I in 0 to C_MB_DBG_PORTS-1 loop
-- if (I = to_integer(unsigned(bits_to_use))) then
-- MB_Debug_Enabled(I) <= '1';
-- end if;
-- end loop; -- I
-- end if;
-- end process Create_MB_Dbg_Port_Enables;
end generate More_Than_One;
Only_One_MB: if (C_MB_DBG_PORTS = 1) generate
MB_Debug_Enabled(0) <= '1';
end generate Only_One_MB;
No_MB: if (C_MB_DBG_PORTS = 0) generate
MB_Debug_Enabled(0) <= '0';
end generate No_MB;
-----------------------------------------------------------------------------
-- UART section
-----------------------------------------------------------------------------
-- Since only one bit can change in the status register at time
-- we don't need to synchronize them with the DRCK clock
status_Reg(7) <= fifo_Data_Present;
status_Reg(6) <= tx_Buffer_Full_I;
status_Reg(5) <= not rx_Data_Present_I;
status_Reg(4) <= rx_Buffer_Full_I;
-- status_Reg(0 to 3) <= (others => '0');
status_Reg(3) <= FSL0_S_Exists;
status_Reg(2) <= FSL0_M_Full;
status_Reg(1) <= FSL_Read_UnderRun;
status_Reg(0) <= FSL_Write_OverRun;
-- Not currently used
FSL_Read_UnderRun <= '0';
No_UART_2 : if (C_USE_UART = 0) generate
uart_TDO <= '0';
end generate No_UART_2;
Have_UARTs : if (C_USE_UART = 1) generate
-- Read UART registers
TDO_Register : process (DRCK) is
begin -- process TDO_Register
if DRCK'event and DRCK = '1' then -- rising clock edge
if (SYNC = '0') then
case Command(CMD_RANGE'RANGE) is
when UART_READ_STATUS =>
tdo_reg <= (others => '0');
tdo_reg(tdo_reg'right-status_reg'right to tdo_reg'right) <= status_Reg;
when others => tdo_reg <= fifo_DOut;
end case;
elsif shifting_Data = '1' then
tdo_reg(tdo_reg'left+1 to tdo_reg'right) <= tdo_reg(tdo_reg'left to tdo_reg'right-1);
tdo_reg(tdo_reg'left) <= '0';
end if;
end if;
end process TDO_Register;
uart_TDO <= tdo_reg(tdo_reg'right);
-----------------------------------------------------------------------------
-- FIFO
-----------------------------------------------------------------------------
RX_FIFO_I : SRL_FIFO
generic map (
C_DATA_BITS => C_UART_WIDTH, -- [natural]
C_DEPTH => 16) -- [natural]
port map (
Clk => OPB_Clk, -- [in std_logic]
Reset => Reset_RX_FIFO, -- [in std_logic]
FIFO_Write => fifo_Write, -- [in std_logic]
Data_In => fifo_Din(0 to C_UART_WIDTH-1), -- [in std_logic_vector(0 to C_DATA_BITS-1)]
FIFO_Read => Read_RX_FIFO, -- [in std_logic]
Data_Out => RX_Data, -- [out std_logic_vector(0 to C_DATA_BITS-1)]
FIFO_Full => rx_Buffer_Full_I, -- [out std_logic]
Data_Exists => rx_Data_Present_I); -- [out std_logic]
RX_Data_Present <= rx_Data_Present_I;
RX_Buffer_Full <= rx_Buffer_Full_I;
TX_FIFO_I : SRL_FIFO
generic map (
C_DATA_BITS => C_UART_WIDTH, -- [natural]
C_DEPTH => 16) -- [natural]
port map (
Clk => OPB_Clk, -- [in std_logic]
Reset => Reset_TX_FIFO, -- [in std_logic]
FIFO_Write => Write_TX_FIFO, -- [in std_logic]
Data_In => TX_Data, -- [in std_logic_vector(0 to C_DATA_BITS-1)]
FIFO_Read => fifo_Read, -- [in std_logic]
Data_Out => fifo_DOut, -- [out std_logic_vector(0 to C_DATA_BITS-1)]
FIFO_Full => TX_Buffer_Full_I, -- [out std_logic]
Data_Exists => fifo_Data_Present); -- [out std_logic]
TX_Buffer_Full <= TX_Buffer_Full_I;
TX_Buffer_Empty <= not fifo_Data_Present;
end generate Have_UARTs;
-----------------------------------------------------------------------------
-- FSL handling
-----------------------------------------------------------------------------
Use_FSL: if (C_USE_FSL /= 0) generate
signal New_FSL_Data : std_logic := '0';
signal Write_to_FSL_En : std_logic;
signal FSL_Data_DRCK : std_logic_vector(0 to C_FSL_DATA_SIZE-1);
-- signal Cnt_31 : std_logic := '0';
signal Cnt_32 : std_logic := '0';
begin
-- Currently no FSL slave interface
FSL0_S_Clk <= '0';
FSL0_S_Read <= '0';
Write_to_FSL_En <= '1' when (Command(CMD_RANGE'RANGE) = MDM_WRITE_TO_FSL) else '0';
New_Data: process (DRCK) is
begin -- process New_Data
if DRCK'event and DRCK = '1' then -- rising clock edge
Cnt_32 <= '0';
New_FSL_Data <= '0';
if (shift_Count(4 downto 0) = "11111") then -- Counted 31 tim
Cnt_32 <= Write_to_FSL_En;
end if;
if (Cnt_32 = '1') then
New_FSL_Data <= Write_to_FSL_En;
FSL_Data_DRCK <= fifo_Din(0 to C_FSL_DATA_SIZE-1);
end if;
end if;
end process New_Data;
---------------------------------------------------------------------------
-- Write to FSL, assumes that OPB_Clk is faster than JTAG Clock
---------------------------------------------------------------------------
Write_FSL_Data: process (OPB_Clk, OPB_Rst) is
variable prev1 : std_logic;
variable prev2 : std_logic;
begin -- process Write_FSL_Data
if OPB_Rst = '1' then -- asynchronous reset (active high)
FSL0_M_Write <= '0';
prev1 := '0';
prev2 := '0';
elsif OPB_Clk'event and OPB_Clk = '1' then -- rising clock edge
FSL0_M_Write <= '0';
if (prev2 = '0' and prev1 = '1') then
FSL0_M_Write <= '1';
end if;
prev2 := prev1;
prev1 := New_FSL_Data;
end if;
end process Write_FSL_Data;
FSL0_M_Data <= FSL_Data_DRCK; -- Will change every 32 JTAG clock so
-- it safe to use it to write in the
-- OPB clock domain since the write
-- strobe is delayed at least one
-- OPB_Clk after the data changes
FSL0_M_Clk <= OPB_Clk;
FSL0_M_Control <= '0'; -- No control mechanism yet
OverRun_Register : process (DRCK) is
begin -- process OverRun_Register
if DRCK'event and DRCK = '1' then -- rising clock edge
if (shifting_Data = '1') and ( Command(CMD_RANGE'RANGE) = UART_READ_STATUS) then
FSL_Write_OverRun <= '0';
end if;
if (New_FSL_Data = '1' and FSL0_M_Full = '1') then
FSL_Write_OverRun <= '1';
end if;
end if;
end process OverRun_Register;
end generate Use_FSL;
No_FSL : if (C_USE_FSL = 0) generate
FSL0_S_Clk <= '0';
FSL0_S_Read <= '0';
FSL0_M_Clk <= '0';
FSL0_M_Write <= '0';
FSL0_M_Data <= (others => '0');
FSL0_M_Control <= '0';
FSL_Write_OverRun <= '0';
end generate No_FSL;
-----------------------------------------------------------------------------
-- Adding signal for debugging using chipscope
-----------------------------------------------------------------------------
jtag_clk <= DRCK;
trig(0) <= data_cmd_n;
trig(1) <= shifting_Data;
trig(2) <= load_command;
trig(3) <= execute;
trig(4) <= Command(2);
trig(5) <= command(3);
trig(6) <= command(4);
trig(7) <= command(5);
data(0) <= data_cmd_n;
data(1) <= shifting_Data;
data(2) <= load_command;
data(3) <= execute;
data(4) <= tdi_reg;
data(5) <= fifo_din(0);
data(6) <= fifo_din(1);
data(7) <= fifo_din(2);
data(8) <= fifo_din(3);
data(9) <= fifo_din(4);
data(10) <= fifo_din(5);
data(11) <= fifo_din(6);
data(12) <= fifo_din(7);
data(13) <= command(1);
data(14) <= command(2);
data(15) <= command(3);
data(16) <= command(4);
data(17) <= command(5);
data(18) <= ext_BRK_i;
data(19) <= Ext_NM_BRK_i;
data(20) <= Debug_SYS_Rst_i;
data(21) <= Debug_Rst_i;
data(23 downto 22) <= (others => '0');
data(31 downto 24) <= "01000010";
end architecture IMP;
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