📄 jtag_control.vhd
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-------------------------------------------------------------------------------
-- $Id: jtag_control.vhd,v 1.1 2004/08/12 01:42:47 khangdao Exp $
-------------------------------------------------------------------------------
-- jtag_control.vhd - Entity and architecture
--
-- ***************************************************************************
-- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This text contains proprietary, confidential **
-- ** information of Xilinx, Inc. , is distributed by **
-- ** under license from Xilinx, Inc., and may be used, **
-- ** copied and/or disclosed only pursuant to the terms **
-- ** of a valid license agreement with Xilinx, Inc. **
-- ** **
-- ** Unmodified source code is guaranteed to place and route, **
-- ** function and run at speed according to the datasheet **
-- ** specification. Source code is provided "as-is", with no **
-- ** obligation on the part of Xilinx to provide support. **
-- ** **
-- ** Xilinx Hotline support of source code IP shall only include **
-- ** standard level Xilinx Hotline support, and will only address **
-- ** issues and questions related to the standard released Netlist **
-- ** version of the core (and thus indirectly, the original core source). **
-- ** **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Support Hotline will only be able **
-- ** to confirm the problem in the Netlist version of the core. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: jtag_control.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- jtag_control.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2004/08/12 01:42:47 $
--
-- History:
-- goran 2003-02-13 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity JTAG_CONTROL is
generic (
C_MB_DBG_PORTS : integer;
C_USE_UART : integer;
C_UART_WIDTH : integer;
C_USE_FSL : integer := 0;
C_FSL_DATA_SIZE : integer := 32;
C_EN_WIDTH : integer := 1
);
port (
-- Global signals
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Clear_Ext_BRK : in std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic := '0';
Debug_SYS_Rst : out std_logic := '0';
Debug_Rst : out std_logic := '0';
Read_RX_FIFO : in std_logic;
Reset_RX_FIFO : in std_logic;
RX_Data : out std_logic_vector(0 to C_UART_WIDTH-1);
RX_Data_Present : out std_logic;
RX_BUFFER_FULL : out std_logic;
Write_TX_FIFO : in std_logic;
Reset_TX_FIFO : in std_logic;
TX_Data : in std_logic_vector(0 to C_UART_WIDTH-1);
TX_Buffer_Full : out std_logic;
TX_Buffer_Empty : out std_logic;
-- MDM signals
TDI : in std_logic;
RESET : in std_logic;
UPDATE : in std_logic;
SHIFT : in std_logic;
SEL : in std_logic;
DRCK : in std_logic;
TDO : out std_logic;
-- MicroBlaze Debug Signals
MB_Debug_Enabled : out std_logic_vector(0 to C_EN_WIDTH-1);
Dbg_Clk : out std_logic;
Dbg_TDI : out std_logic;
Dbg_TDO : in std_logic;
Dbg_Reg_En : out std_logic_vector(0 to 4);
Dbg_Capture : out std_logic;
Dbg_Update : out std_logic;
FSL0_S_Clk : out std_logic;
FSL0_S_Read : out std_logic;
FSL0_S_Data : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_S_Control : in std_logic;
FSL0_S_Exists : in std_logic;
FSL0_M_Clk : out std_logic;
FSL0_M_Write : out std_logic;
FSL0_M_Data : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_M_Control : out std_logic;
FSL0_M_Full : in std_logic;
jtag_clk : out std_logic;
trig : out std_logic_vector(7 downto 0);
data : out std_logic_vector(31 downto 0)
);
end entity JTAG_CONTROL;
library unisim;
use unisim.vcomponents.all;
library Opb_mdm_v2_01_a;
use Opb_mdm_v2_01_a.SRL_FIFO;
architecture IMP of JTAG_CONTROL is
component SRL_FIFO is
generic (
C_DATA_BITS : natural;
C_DEPTH : natural);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic);
end component SRL_FIFO;
-- component FDC is
-- port (
-- Q : out std_logic;
-- C : in std_logic;
-- D : in std_logic;
-- CLR : in std_logic
-- );
-- end component FDC;
-- component FDRE is
-- port (
-- Q : out std_logic;
-- C : in std_logic;
-- CE : in std_logic;
-- D : in std_logic;
-- R : in std_logic
-- );
-- end component FDRE;
-- component FDE is
-- port (
-- Q : out std_logic;
-- C : in std_logic;
-- CE : in std_logic;
-- D : in std_logic
-- );
-- end component FDE;
-- component FDR is
-- port (
-- Q : out std_logic;
-- C : in std_logic;
-- D : in std_logic;
-- R : in std_logic
-- );
-- end component FDR;
-- component FDRSE is
-- port (
-- Q : out std_logic;
-- C : in std_logic;
-- CE : in std_logic;
-- D : in std_logic;
-- R : in std_logic;
-- S : in std_logic
-- );
-- end component FDRSE;
-- component SRL16E is
-- -- pragma translate_off
-- generic (
-- INIT : bit_vector(15 downto 0)
-- );
-- -- pragma translate_on
-- port (
-- CE : in std_logic;
-- D : in std_logic;
-- Clk : in std_logic;
-- A0 : in std_logic;
-- A1 : in std_logic;
-- A2 : in std_logic;
-- A3 : in std_logic;
-- Q : out std_logic);
-- end component SRL16E;
function log2(x : natural) return integer is
variable i : integer := 0;
begin
if x = 0 then return 0;
else
while 2**i < x loop
i := i+1;
end loop;
return i;
end if;
end function log2;
constant No_MicroBlazes : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(C_MB_DBG_PORTS, 8));
constant No_HW_PORTS : std_logic_vector(3 downto 0) := "0000";
constant VERSION_I : std_logic_vector(3 downto 0) := "0011";
constant Config_Init_Word_S : std_logic_vector(15 downto 0) := (No_MicroBlazes &
No_HW_PORTS &
VERSION_I);
constant Config_Init_Word : bit_vector(15 downto 0) := to_bitvector(Config_Init_Word_S);
constant HAVE_UART : std_logic_vector(0 to 0) := std_logic_vector(to_unsigned(C_USE_UART, 1));
constant UART_WIDTH : std_logic_vector(0 to 4) := std_logic_vector(to_unsigned(C_UART_WIDTH-1, 5));
constant HAVE_FSL : std_logic_vector(0 to 0) := std_logic_vector(to_unsigned(C_USE_FSL, 1));
constant MAGIC_STRING : std_logic_vector(0 to 7) := "01000010";
constant Config_Init_Word2_S : std_logic_vector(15 downto 0) := (MAGIC_STRING &
HAVE_FSL & '0' &
HAVE_UART & UART_WIDTH);
constant Config_Init_Word2 : bit_vector(15 downto 0) := to_bitvector(Config_Init_Word2_S);
function itohex (int : natural; len : natural) return string is
type table is array (0 to 15) of character;
constant LUT : table :=
('0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F');
variable str : string(1 to len);
variable rest, temp : natural;
begin
temp := int;
for I in Len downto 1 loop
rest := temp mod 16;
temp := temp / 16;
str(I) := LUT(rest);
end loop; -- I
return str;
end function itohex;
signal config_TDO_1 : std_logic;
signal config_TDO_2 : std_logic;
signal config_TDO : std_logic;
attribute INIT : string;
attribute INIT of SRL16E_1 : label is itohex(to_integer(unsigned(Config_Init_Word_S)), 4);
attribute INIT of SRL16E_2 : label is itohex(to_integer(unsigned(Config_Init_Word2_S)), 4);
-----------------------------------------------------------------------------
-- JTAG signals
-----------------------------------------------------------------------------
signal tdi_reg : std_logic;
signal data_cmd : std_logic;
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