bram1_elaborate.vhd

实用的程序代码

LIBRARY unisim;
USE unisim.vcomponents.ALL;

--------------------------------------------------------------------------------
-- bram1_elaborate.vhd
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY bram1_elaborate IS
GENERIC (
	C_PORTA_AWIDTH : INTEGER := 32;
	C_PORTA_DWIDTH : INTEGER := 64;
	C_PORTB_AWIDTH : INTEGER := 32;
	C_PORTB_DWIDTH : INTEGER := 64;
	C_NUM_WE : INTEGER := 8);
PORT (
	-- instance GLOBAL
	BRAM_Addr_B : IN STD_LOGIC_VECTOR(0 TO 31);
	BRAM_Dout_A : IN STD_LOGIC_VECTOR(0 TO 63);
	BRAM_EN_A : IN STD_LOGIC;
	BRAM_Dout_B : IN STD_LOGIC_VECTOR(0 TO 63);
	BRAM_EN_B : IN STD_LOGIC;
	BRAM_Din_A : OUT STD_LOGIC_VECTOR(0 TO 63);
	BRAM_Din_B : OUT STD_LOGIC_VECTOR(0 TO 63);
	BRAM_Clk_A : IN STD_LOGIC;
	BRAM_WEN_A : IN STD_LOGIC_VECTOR(0 TO 7);
	BRAM_WEN_B : IN STD_LOGIC_VECTOR(0 TO 7);
	BRAM_Clk_B : IN STD_LOGIC;
	BRAM_Rst_A : IN STD_LOGIC;
	BRAM_Rst_B : IN STD_LOGIC;
	BRAM_Addr_A : IN STD_LOGIC_VECTOR(0 TO 31));
END bram1_elaborate;

ARCHITECTURE IMP OF bram1_elaborate IS

--------------------------------------------------------------------------------
COMPONENT RAMB16_S4_S4 IS
PORT (
	CLKB : IN STD_LOGIC;
	ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
	ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
	DOA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	DOB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	ENA : IN STD_LOGIC;
	SSRA : IN STD_LOGIC;
	ENB : IN STD_LOGIC;
	SSRB : IN STD_LOGIC;
	DIA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	DIB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	WEA : IN STD_LOGIC;
	WEB : IN STD_LOGIC;
	CLKA : IN STD_LOGIC);
END COMPONENT;

--------------------------------------------------------------------------------
-- internal signals
--------------------------------------------------------------------------------

	SIGNAL dina : STD_LOGIC_VECTOR(63 DOWNTO 0);

	SIGNAL dinb : STD_LOGIC_VECTOR(63 DOWNTO 0);

	SIGNAL douta : STD_LOGIC_VECTOR(63 DOWNTO 0);

	SIGNAL doutb : STD_LOGIC_VECTOR(63 DOWNTO 0);

	SIGNAL net_gnd0 : STD_LOGIC;

BEGIN

--------------------------------------------------------------------------------
-- Power assignments
net_gnd0 <= '0';
--------------------------------------------------------------------------------
-- Constant assignments
--------------------------------------------------------------------------------
-- Top-level port assignments
dina <= BRAM_Dout_A;
dinb <= BRAM_Dout_B;
BRAM_Din_A <= douta;
BRAM_Din_B <= doutb;
--------------------------------------------------------------------------------
-- Lower-level assignments
--------------------------------------------------------------------------------
-- Tri-state assignments

--------------------------------------------------------------------------------
ramb16_s4_s4_0 : RAMB16_S4_S4
PORT MAP (
	CLKB => BRAM_Clk_B,
	ADDRA => BRAM_Addr_A(17 TO 28),
	ADDRB => BRAM_Addr_B(17 TO 28),
	DOA => douta(63 DOWNTO 60),
	DOB => doutb(63 DOWNTO 60),
	ENA => BRAM_EN_A,
	SSRA => net_gnd0,
	ENB => BRAM_EN_B,
	SSRB => net_gnd0,
	DIA => dina(63 DOWNTO 60),
	DIB => dinb(63 DOWNTO 60),
	WEA => BRAM_WEN_A(0),
	WEB => BRAM_WEN_B(0),
	CLKA => BRAM_Clk_A);

--------------------------------------------------------------------------------
ramb16_s4_s4_1 : RAMB16_S4_S4
PORT MAP (
	CLKB => BRAM_Clk_B,
	ADDRA => BRAM_Addr_A(17 TO 28),
	ADDRB => BRAM_Addr_B(17 TO 28),
	DOA => douta(59 DOWNTO 56),
	DOB => doutb(59 DOWNTO 56),
	ENA => BRAM_EN_A,
	SSRA => net_gnd0,
	ENB => BRAM_EN_B,
	SSRB => net_gnd0,
	DIA => dina(59 DOWNTO 56),
	DIB => dinb(59 DOWNTO 56),
	WEA => BRAM_WEN_A(0),
	WEB => BRAM_WEN_B(0),
	CLKA => BRAM_Clk_A);

--------------------------------------------------------------------------------
ramb16_s4_s4_2 : RAMB16_S4_S4
PORT MAP (
	CLKB => BRAM_Clk_B,
	ADDRA => BRAM_Addr_A(17 TO 28),
	ADDRB => BRAM_Addr_B(17 TO 28),
	DOA => douta(55 DOWNTO 52),
	DOB => doutb(55 DOWNTO 52),
	ENA => BRAM_EN_A,
	SSRA => net_gnd0,
	ENB => BRAM_EN_B,
	SSRB => net_gnd0,
	DIA => dina(55 DOWNTO 52),
	DIB => dinb(55 DOWNTO 52),
	WEA => BRAM_WEN_A(1),
	WEB => BRAM_WEN_B(1),
	CLKA => BRAM_Clk_A);

--------------------------------------------------------------------------------
ramb16_s4_s4_3 : RAMB16_S4_S4
PORT MAP (
	CLKB => BRAM_Clk_B,
	ADDRA => BRAM_Addr_A(17 TO 28),
	ADDRB => BRAM_Addr_B(17 TO 28),
	DOA => douta(51 DOWNTO 48),
	DOB => doutb(51 DOWNTO 48),
	ENA => BRAM_EN_A,
	SSRA => net_gnd0,
	ENB => BRAM_EN_B,
	SSRB => net_gnd0,
	DIA => dina(51 DOWNTO 48),
	DIB => dinb(51 DOWNTO 48),
	WEA => BRAM_WEN_A(1),
	WEB => BRAM_WEN_B(1),
	CLKA => BRAM_Clk_A);

--------------------------------------------------------------------------------
ramb16_s4_s4_4 : RAMB16_S4_S4
PORT MAP (
	CLKB => BRAM_Clk_B,
	ADDRA => BRAM_Addr_A(17 TO 28),
	ADDRB => BRAM_Addr_B(17 TO 28),
	DOA => douta(47 DOWNTO 44),
	DOB => doutb(47 DOWNTO 44),
	ENA => BRAM_EN_A,
	SSRA => net_gnd0,
	ENB => BRAM_EN_B,
	SSRB => net_gnd0,
	DIA => dina(47 DOWNTO 44),
	DIB => dinb(47 DOWNTO 44),
	WEA => BRAM_WEN_A(2),
	WEB => BRAM_WEN_B(2),
	CLKA => BRAM_Clk_A);

--------------------------------------------------------------------------------
ramb16_s4_s4_5 : RAMB16_S4_S4
PORT MAP (
	CLKB => BRAM_Clk_B,
	ADDRA => BRAM_Addr_A(17 TO 28),
	ADDRB => BRAM_Addr_B(17 TO 28),
	DOA => douta(43 DOWNTO 40),
	DOB => doutb(43 DOWNTO 40),
	ENA => BRAM_EN_A,
	SSRA => net_gnd0,
	ENB => BRAM_EN_B,
	SSRB => net_gnd0,
	DIA => dina(43 DOWNTO 40),
	DIB => dinb(43 DOWNTO 40),
	WEA => BRAM_WEN_A(2),
	WEB => BRAM_WEN_B(2),
	CLKA => BRAM_Clk_A);

--------------------------------------------------------------------------------
ramb16_s4_s4_6 : RAMB16_S4_S4
PORT MAP (
	CLKB => BRAM_Clk_B,
	ADDRA => BRAM_Addr_A(17 TO 28),
	ADDRB => BRAM_Addr_B(17 TO 28),
	DOA => douta(39 DOWNTO 36),
	DOB => doutb(39 DOWNTO 36),
	ENA => BRAM_EN_A,
	SSRA => net_gnd0,
	ENB => BRAM_EN_B,
	SSRB => net_gnd0,
	DIA => dina(39 DOWNTO 36),
	DIB => dinb(39 DOWNTO 36),
	WEA => BRAM_WEN_A(3),
	WEB => BRAM_WEN_B(3),
	CLKA => BRAM_Clk_A);

--------------------------------------------------------------------------------
ramb16_s4_s4_7 : RAMB16_S4_S4
PORT MAP (
	CLKB => BRAM_Clk_B,
	ADDRA => BRAM_Addr_A(17 TO 28),
	ADDRB => BRAM_Addr_B(17 TO 28),
	DOA => douta(35 DOWNTO 32),
	DOB => doutb(35 DOWNTO 32),
	ENA => BRAM_EN_A,
	SSRA => net_gnd0,
	ENB => BRAM_EN_B,
	SSRB => net_gnd0,
	DIA => dina(35 DOWNTO 32),
	DIB => dinb(35 DOWNTO 32),
	WEA => BRAM_WEN_A(3),
	WEB => BRAM_WEN_B(3),
	CLKA => BRAM_Clk_A);

--------------------------------------------------------------------------------
ramb16_s4_s4_8 : RAMB16_S4_S4
PORT MAP (
	CLKB => BRAM_Clk_B,
	ADDRA => BRAM_Addr_A(17 TO 28),
	ADDRB => BRAM_Addr_B(17 TO 28),
	DOA => douta(31 DOWNTO 28),
	DOB => doutb(31 DOWNTO 28),
	ENA => BRAM_EN_A,
	SSRA => net_gnd0,
	ENB => BRAM_EN_B,
	SSRB => net_gnd0,
	DIA => dina(31 DOWNTO 28),
	DIB => dinb(31 DOWNTO 28),
	WEA => BRAM_WEN_A(4),
	WEB => BRAM_WEN_B(4),
	CLKA => BRAM_Clk_A);

--------------------------------------------------------------------------------
ramb16_s4_s4_9 : RAMB16_S4_S4
PORT MAP (
	CLKB => BRAM_Clk_B,
	ADDRA => BRAM_Addr_A(17 TO 28),
	ADDRB => BRAM_Addr_B(17 TO 28),
	DOA => douta(27 DOWNTO 24),
	DOB => doutb(27 DOWNTO 24),
	ENA => BRAM_EN_A,
	SSRA => net_gnd0,
	ENB => BRAM_EN_B,
	SSRB => net_gnd0,
	DIA => dina(27 DOWNTO 24),
	DIB => dinb(27 DOWNTO 24),
	WEA => BRAM_WEN_A(4),
	WEB => BRAM_WEN_B(4),
	CLKA => BRAM_Clk_A);

--------------------------------------------------------------------------------
ramb16_s4_s4_10 : RAMB16_S4_S4
PORT MAP (
	CLKB => BRAM_Clk_B,
	ADDRA => BRAM_Addr_A(17 TO 28),
	ADDRB => BRAM_Addr_B(17 TO 28),
	DOA => douta(23 DOWNTO 20),
	DOB => doutb(23 DOWNTO 20),
	ENA => BRAM_EN_A,
	SSRA => net_gnd0,
	ENB => BRAM_EN_B,
	SSRB => net_gnd0,
	DIA => dina(23 DOWNTO 20),
	DIB => dinb(23 DOWNTO 20),
	WEA => BRAM_WEN_A(5),
	WEB => BRAM_WEN_B(5),
	CLKA => BRAM_Clk_A);

--------------------------------------------------------------------------------
ramb16_s4_s4_11 : RAMB16_S4_S4
PORT MAP (
	CLKB => BRAM_Clk_B,
	ADDRA => BRAM_Addr_A(17 TO 28),
	ADDRB => BRAM_Addr_B(17 TO 28),
	DOA => douta(19 DOWNTO 16),
	DOB => doutb(19 DOWNTO 16),
	ENA => BRAM_EN_A,
	SSRA => net_gnd0,
	ENB => BRAM_EN_B,
	SSRB => net_gnd0,
	DIA => dina(19 DOWNTO 16),
	DIB => dinb(19 DOWNTO 16),
	WEA => BRAM_WEN_A(5),
	WEB => BRAM_WEN_B(5),
	CLKA => BRAM_Clk_A);

--------------------------------------------------------------------------------
ramb16_s4_s4_12 : RAMB16_S4_S4
PORT MAP (
	CLKB => BRAM_Clk_B,
	ADDRA => BRAM_Addr_A(17 TO 28),
	ADDRB => BRAM_Addr_B(17 TO 28),
	DOA => douta(15 DOWNTO 12),
	DOB => doutb(15 DOWNTO 12),
	ENA => BRAM_EN_A,
	SSRA => net_gnd0,
	ENB => BRAM_EN_B,
	SSRB => net_gnd0,
	DIA => dina(15 DOWNTO 12),
	DIB => dinb(15 DOWNTO 12),
	WEA => BRAM_WEN_A(6),
	WEB => BRAM_WEN_B(6),
	CLKA => BRAM_Clk_A);

--------------------------------------------------------------------------------
ramb16_s4_s4_13 : RAMB16_S4_S4
PORT MAP (
	CLKB => BRAM_Clk_B,
	ADDRA => BRAM_Addr_A(17 TO 28),
	ADDRB => BRAM_Addr_B(17 TO 28),
	DOA => douta(11 DOWNTO 8),
	DOB => doutb(11 DOWNTO 8),
	ENA => BRAM_EN_A,
	SSRA => net_gnd0,
	ENB => BRAM_EN_B,
	SSRB => net_gnd0,
	DIA => dina(11 DOWNTO 8),
	DIB => dinb(11 DOWNTO 8),
	WEA => BRAM_WEN_A(6),
	WEB => BRAM_WEN_B(6),
	CLKA => BRAM_Clk_A);

--------------------------------------------------------------------------------
ramb16_s4_s4_14 : RAMB16_S4_S4
PORT MAP (
	CLKB => BRAM_Clk_B,
	ADDRA => BRAM_Addr_A(17 TO 28),
	ADDRB => BRAM_Addr_B(17 TO 28),
	DOA => douta(7 DOWNTO 4),
	DOB => doutb(7 DOWNTO 4),
	ENA => BRAM_EN_A,
	SSRA => net_gnd0,
	ENB => BRAM_EN_B,
	SSRB => net_gnd0,
	DIA => dina(7 DOWNTO 4),
	DIB => dinb(7 DOWNTO 4),
	WEA => BRAM_WEN_A(7),
	WEB => BRAM_WEN_B(7),
	CLKA => BRAM_Clk_A);

--------------------------------------------------------------------------------
ramb16_s4_s4_15 : RAMB16_S4_S4
PORT MAP (
	CLKB => BRAM_Clk_B,
	ADDRA => BRAM_Addr_A(17 TO 28),
	ADDRB => BRAM_Addr_B(17 TO 28),
	DOA => douta(3 DOWNTO 0),
	DOB => doutb(3 DOWNTO 0),
	ENA => BRAM_EN_A,
	SSRA => net_gnd0,
	ENB => BRAM_EN_B,
	SSRB => net_gnd0,
	DIA => dina(3 DOWNTO 0),
	DIB => dinb(3 DOWNTO 0),
	WEA => BRAM_WEN_A(7),
	WEB => BRAM_WEN_B(7),
	CLKA => BRAM_Clk_A);

END ARCHITECTURE IMP;