time_sim.vhd

实用的程序代码

-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 16:20:54 1998
-- Design file: time_sim.nga
-- Device: 4005epc84-2
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity MUX_TBUF16 is
  port (
    A : in STD_LOGIC := 'X' ;
    B : in STD_LOGIC := 'X' ;
    C : in STD_LOGIC := 'X' ;
    D : in STD_LOGIC := 'X' ;
    E : in STD_LOGIC := 'X' ;
    F : in STD_LOGIC := 'X' ;
    G : in STD_LOGIC := 'X' ;
    H : in STD_LOGIC := 'X' ;
    I : in STD_LOGIC := 'X' ;
    J : in STD_LOGIC := 'X' ;
    K : in STD_LOGIC := 'X' ;
    L : in STD_LOGIC := 'X' ;
    M : in STD_LOGIC := 'X' ;
    N : in STD_LOGIC := 'X' ;
    O : in STD_LOGIC := 'X' ;
    P : in STD_LOGIC := 'X' ;
    SIG : out STD_LOGIC ;
    SEL : in  STD_LOGIC_VECTOR ( 15 downto 0 )
  ) ;
end MUX_TBUF16 ;

architecture STRUCTURE of MUX_TBUF16 is
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal N711 , N606 , SIG_TRI_ENABLE407 , N599 , SIG_TRI_ENABLE183 , N601 , 
  SIG_TRI_ENABLE247 , N607 , SIG_TRI_ENABLE439 , N602 , SIG_TRI_ENABLE279 , 
  N608 , SIG_TRI_ENABLE471 , N605 , SIG_TRI_ENABLE375 , N600 , 
  SIG_TRI_ENABLE215 , N603 , SIG_TRI_ENABLE311 , N598 , SIG_TRI_ENABLE151 , 
  N595 , SIG_TRI_ENABLE55 , N596 , SIG_TRI_ENABLE87 , N594 , SIG_TRI_ENABLE , 
  N609 , SIG_TRI_ENABLE503 , N604 , SIG_TRI_ENABLE343 , N597 , 
  SIG_TRI_ENABLE119 , U314_1I20_GTS_TRI , SIG_TRI13_2_INV , SIG_TRI6_2_INV , 
  SIG_TRI8_2_INV , SIG_TRI14_2_INV , SIG_TRI9_2_INV , SIG_TRI15_2_INV , 
  SIG_TRI12_2_INV , SIG_TRI7_2_INV , SIG_TRI10_2_INV , SIG_TRI5_2_INV , 
  SIG_TRI2_2_INV , SIG_TRI3_2_INV , SIG_TRI_2_INV , SIG_TRI16_2_INV , 
  SIG_TRI11_2_INV , SIG_TRI4_2_INV , U314_1I20_GTS_TRI_2_INV , GTS : STD_LOGIC ;
  begin
    SIG_TRI13 : X_TRI 
      port map ( I => N606 , O => N711 , CTL => SIG_TRI13_2_INV ) ;
    SIG_TRI6 : X_TRI 
      port map ( I => N599 , O => N711 , CTL => SIG_TRI6_2_INV ) ;
    SIG_TRI8 : X_TRI 
      port map ( I => N601 , O => N711 , CTL => SIG_TRI8_2_INV ) ;
    SIG_TRI14 : X_TRI 
      port map ( I => N607 , O => N711 , CTL => SIG_TRI14_2_INV ) ;
    SIG_TRI9 : X_TRI 
      port map ( I => N602 , O => N711 , CTL => SIG_TRI9_2_INV ) ;
    SIG_TRI15 : X_TRI 
      port map ( I => N608 , O => N711 , CTL => SIG_TRI15_2_INV ) ;
    SIG_TRI12 : X_TRI 
      port map ( I => N605 , O => N711 , CTL => SIG_TRI12_2_INV ) ;
    SIG_TRI7 : X_TRI 
      port map ( I => N600 , O => N711 , CTL => SIG_TRI7_2_INV ) ;
    SIG_TRI10 : X_TRI 
      port map ( I => N603 , O => N711 , CTL => SIG_TRI10_2_INV ) ;
    SIG_TRI5 : X_TRI 
      port map ( I => N598 , O => N711 , CTL => SIG_TRI5_2_INV ) ;
    SIG_TRI2 : X_TRI 
      port map ( I => N595 , O => N711 , CTL => SIG_TRI2_2_INV ) ;
    SIG_TRI3 : X_TRI 
      port map ( I => N596 , O => N711 , CTL => SIG_TRI3_2_INV ) ;
    SIG_TRI : X_TRI 
      port map ( I => N594 , O => N711 , CTL => SIG_TRI_2_INV ) ;
    SIG_TRI16 : X_TRI 
      port map ( I => N609 , O => N711 , CTL => SIG_TRI16_2_INV ) ;
    SIG_TRI11 : X_TRI 
      port map ( I => N604 , O => N711 , CTL => SIG_TRI11_2_INV ) ;
    SIG_TRI4 : X_TRI 
      port map ( I => N597 , O => N711 , CTL => SIG_TRI4_2_INV ) ;
    U282 : X_BUF 
      port map ( I => SEL(15) , O => SIG_TRI_ENABLE503 ) ;
    U283 : X_BUF 
      port map ( I => SEL(14) , O => SIG_TRI_ENABLE471 ) ;
    U284 : X_BUF 
      port map ( I => SEL(13) , O => SIG_TRI_ENABLE439 ) ;
    U285 : X_BUF 
      port map ( I => SEL(12) , O => SIG_TRI_ENABLE407 ) ;
    U286 : X_BUF 
      port map ( I => SEL(11) , O => SIG_TRI_ENABLE375 ) ;
    U287 : X_BUF 
      port map ( I => SEL(10) , O => SIG_TRI_ENABLE343 ) ;
    U288 : X_BUF 
      port map ( I => SEL(9) , O => SIG_TRI_ENABLE311 ) ;
    U289 : X_BUF 
      port map ( I => SEL(8) , O => SIG_TRI_ENABLE279 ) ;
    U290 : X_BUF 
      port map ( I => SEL(7) , O => SIG_TRI_ENABLE247 ) ;
    U291 : X_BUF 
      port map ( I => SEL(6) , O => SIG_TRI_ENABLE215 ) ;
    U292 : X_BUF 
      port map ( I => SEL(5) , O => SIG_TRI_ENABLE183 ) ;
    U293 : X_BUF 
      port map ( I => SEL(4) , O => SIG_TRI_ENABLE151 ) ;
    U294 : X_BUF 
      port map ( I => SEL(3) , O => SIG_TRI_ENABLE119 ) ;
    U295 : X_BUF 
      port map ( I => SEL(2) , O => SIG_TRI_ENABLE87 ) ;
    U296 : X_BUF 
      port map ( I => SEL(1) , O => SIG_TRI_ENABLE55 ) ;
    U297 : X_BUF 
      port map ( I => SEL(0) , O => SIG_TRI_ENABLE ) ;
    U298 : X_BUF 
      port map ( I => A , O => N594 ) ;
    U299 : X_BUF 
      port map ( I => B , O => N595 ) ;
    U300 : X_BUF 
      port map ( I => C , O => N596 ) ;
    U301 : X_BUF 
      port map ( I => D , O => N597 ) ;
    U302 : X_BUF 
      port map ( I => E , O => N598 ) ;
    U303 : X_BUF 
      port map ( I => F , O => N599 ) ;
    U304 : X_BUF 
      port map ( I => G , O => N600 ) ;
    U305 : X_BUF 
      port map ( I => H , O => N601 ) ;
    U306 : X_BUF 
      port map ( I => I , O => N602 ) ;
    U307 : X_BUF 
      port map ( I => J , O => N603 ) ;
    U308 : X_BUF 
      port map ( I => K , O => N604 ) ;
    U309 : X_BUF 
      port map ( I => L , O => N605 ) ;
    U310 : X_BUF 
      port map ( I => M , O => N606 ) ;
    U311 : X_BUF 
      port map ( I => N , O => N607 ) ;
    U312 : X_BUF 
      port map ( I => O , O => N608 ) ;
    U313 : X_BUF 
      port map ( I => P , O => N609 ) ;
    U314_1I20 : X_BUF 
      port map ( I => N711 , O => U314_1I20_GTS_TRI ) ;
    U314_1I20_GTS_TRI_0 : X_TRI 
      port map ( I => U314_1I20_GTS_TRI , O => SIG , 
      CTL => U314_1I20_GTS_TRI_2_INV ) ;
    SIG_TRI13_2_INV_1 : X_INV 
      port map ( I => SIG_TRI_ENABLE407 , O => SIG_TRI13_2_INV ) ;
    SIG_TRI6_2_INV_2 : X_INV 
      port map ( I => SIG_TRI_ENABLE183 , O => SIG_TRI6_2_INV ) ;
    SIG_TRI8_2_INV_3 : X_INV 
      port map ( I => SIG_TRI_ENABLE247 , O => SIG_TRI8_2_INV ) ;
    SIG_TRI14_2_INV_4 : X_INV 
      port map ( I => SIG_TRI_ENABLE439 , O => SIG_TRI14_2_INV ) ;
    SIG_TRI9_2_INV_5 : X_INV 
      port map ( I => SIG_TRI_ENABLE279 , O => SIG_TRI9_2_INV ) ;
    SIG_TRI15_2_INV_6 : X_INV 
      port map ( I => SIG_TRI_ENABLE471 , O => SIG_TRI15_2_INV ) ;
    SIG_TRI12_2_INV_7 : X_INV 
      port map ( I => SIG_TRI_ENABLE375 , O => SIG_TRI12_2_INV ) ;
    SIG_TRI7_2_INV_8 : X_INV 
      port map ( I => SIG_TRI_ENABLE215 , O => SIG_TRI7_2_INV ) ;
    SIG_TRI10_2_INV_9 : X_INV 
      port map ( I => SIG_TRI_ENABLE311 , O => SIG_TRI10_2_INV ) ;
    SIG_TRI5_2_INV_10 : X_INV 
      port map ( I => SIG_TRI_ENABLE151 , O => SIG_TRI5_2_INV ) ;
    SIG_TRI2_2_INV_11 : X_INV 
      port map ( I => SIG_TRI_ENABLE55 , O => SIG_TRI2_2_INV ) ;
    SIG_TRI3_2_INV_12 : X_INV 
      port map ( I => SIG_TRI_ENABLE87 , O => SIG_TRI3_2_INV ) ;
    SIG_TRI_2_INV_13 : X_INV 
      port map ( I => SIG_TRI_ENABLE , O => SIG_TRI_2_INV ) ;
    SIG_TRI16_2_INV_14 : X_INV 
      port map ( I => SIG_TRI_ENABLE503 , O => SIG_TRI16_2_INV ) ;
    SIG_TRI11_2_INV_15 : X_INV 
      port map ( I => SIG_TRI_ENABLE343 , O => SIG_TRI11_2_INV ) ;
    SIG_TRI4_2_INV_16 : X_INV 
      port map ( I => SIG_TRI_ENABLE119 , O => SIG_TRI4_2_INV ) ;
    U314_1I20_GTS_TRI_2_INV_17 : X_INV 
      port map ( I => GTS , O => U314_1I20_GTS_TRI_2_INV ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;