time_sim.vhd

实用的程序代码

-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 16:26:28 1998
-- Design file: time_sim.nga
-- Device: 4005epc84-2
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity MUX_GATE16 is
  port (
    A : in STD_LOGIC := 'X' ;
    B : in STD_LOGIC := 'X' ;
    C : in STD_LOGIC := 'X' ;
    D : in STD_LOGIC := 'X' ;
    E : in STD_LOGIC := 'X' ;
    F : in STD_LOGIC := 'X' ;
    G : in STD_LOGIC := 'X' ;
    H : in STD_LOGIC := 'X' ;
    I : in STD_LOGIC := 'X' ;
    J : in STD_LOGIC := 'X' ;
    K : in STD_LOGIC := 'X' ;
    L : in STD_LOGIC := 'X' ;
    M : in STD_LOGIC := 'X' ;
    N : in STD_LOGIC := 'X' ;
    O : in STD_LOGIC := 'X' ;
    P : in STD_LOGIC := 'X' ;
    SIG : out STD_LOGIC ;
    SEL : in  STD_LOGIC_VECTOR ( 3 downto 0 )
  ) ;
end MUX_GATE16 ;

architecture STRUCTURE of MUX_GATE16 is
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal N51 , N52 , N53 , N54 , N55 , N56 , N57 , N58 , N59 , N60 , N61 , N62 
  , N63 , N64 , N65 , N66 , N67 , N68 , N69 , N70 , N186 , N147 , N148 , N149 , 
  N123 , N150 , N152 , N151 , N122 , N153 , N154 , N155 , N120 , N156 , N158 , 
  N157 , N119 , N159 , N168 , N161 , N169 , N160 , N164 , N163 , N162 , N124 , 
  N167 , N166 , N165 , N121 , N176 , N177 , N170 , N171 , N172 , N173 , N175 , 
  N174 , N185 , N184 , N178 , N180 , N179 , N181 , N182 , N183 , 
  U124_1I20_GTS_TRI , U128_2_0 , U132_2_0 , U136_2_0 , U140_2_0 , U147_2_0 , 
  U151_2_0 , U153_2_0 , U157_2_0 , U161_2_0 , U162_2_0 , U166_2_0 , U170_2_0 , 
  U126_2_INV , U127_2_INV , U130_2_INV , U134_2_INV , U135_2_INV , U138_2_INV , 
  U142_2_INV , U144_2_INV , U148_2_INV , U152_2_INV , U155_2_INV , U156_2_INV , 
  U159_2_INV , U164_2_INV , U168_2_INV , U169_2_INV , U128_N123_2_INV , 
  U136_N120_2_INV , U153_N124_2_INV , U157_N177_2_INV , U162_N121_2_INV , 
  U170_N184_2_INV , U124_1I20_GTS_TRI_2_INV , GTS : STD_LOGIC ;
  begin
    U104 : X_BUF 
      port map ( I => SEL(3) , O => N51 ) ;
    U105 : X_BUF 
      port map ( I => SEL(2) , O => N52 ) ;
    U106 : X_BUF 
      port map ( I => SEL(1) , O => N53 ) ;
    U107 : X_BUF 
      port map ( I => SEL(0) , O => N54 ) ;
    U108 : X_BUF 
      port map ( I => A , O => N55 ) ;
    U109 : X_BUF 
      port map ( I => B , O => N56 ) ;
    U110 : X_BUF 
      port map ( I => C , O => N57 ) ;
    U111 : X_BUF 
      port map ( I => D , O => N58 ) ;
    U112 : X_BUF 
      port map ( I => E , O => N59 ) ;
    U113 : X_BUF 
      port map ( I => F , O => N60 ) ;
    U114 : X_BUF 
      port map ( I => G , O => N61 ) ;
    U115 : X_BUF 
      port map ( I => H , O => N62 ) ;
    U116 : X_BUF 
      port map ( I => I , O => N63 ) ;
    U117 : X_BUF 
      port map ( I => J , O => N64 ) ;
    U118 : X_BUF 
      port map ( I => K , O => N65 ) ;
    U119 : X_BUF 
      port map ( I => L , O => N66 ) ;
    U120 : X_BUF 
      port map ( I => M , O => N67 ) ;
    U121 : X_BUF 
      port map ( I => N , O => N68 ) ;
    U122 : X_BUF 
      port map ( I => O , O => N69 ) ;
    U123 : X_BUF 
      port map ( I => P , O => N70 ) ;
    U125 : X_INV 
      port map ( I => N54 , O => N147 ) ;
    U126 : X_OR2 
      port map ( I0 => N147 , I1 => N68 , O => U126_2_INV ) ;
    U127 : X_OR2 
      port map ( I0 => N67 , I1 => N54 , O => U127_2_INV ) ;
    U129 : X_INV 
      port map ( I => N70 , O => N150 ) ;
    U130 : X_AND2 
      port map ( I0 => N54 , I1 => N150 , O => U130_2_INV ) ;
    U131 : X_OR2 
      port map ( I0 => N69 , I1 => N54 , O => N151 ) ;
    U133 : X_INV 
      port map ( I => N54 , O => N153 ) ;
    U134 : X_OR2 
      port map ( I0 => N153 , I1 => N60 , O => U134_2_INV ) ;
    U135 : X_OR2 
      port map ( I0 => N59 , I1 => N54 , O => U135_2_INV ) ;
    U137 : X_INV 
      port map ( I => N62 , O => N156 ) ;
    U138 : X_AND2 
      port map ( I0 => N54 , I1 => N156 , O => U138_2_INV ) ;
    U139 : X_OR2 
      port map ( I0 => N61 , I1 => N54 , O => N157 ) ;
    U141 : X_INV 
      port map ( I => N168 , O => N159 ) ;
    U142 : X_AND2 
      port map ( I0 => N51 , I1 => N169 , O => U142_2_INV ) ;
    U143 : X_OR2 
      port map ( I0 => N51 , I1 => N159 , O => N160 ) ;
    U144 : X_AND2 
      port map ( I0 => N160 , I1 => N161 , O => U144_2_INV ) ;
    U145 : X_INV 
      port map ( I => N163 , O => N164 ) ;
    U146 : X_INV 
      port map ( I => N52 , O => N162 ) ;
    U148 : X_OR2 
      port map ( I0 => N164 , I1 => N124 , O => U148_2_INV ) ;
    U149 : X_INV 
      port map ( I => N166 , O => N167 ) ;
    U150 : X_INV 
      port map ( I => N52 , O => N165 ) ;
    U152 : X_OR2 
      port map ( I0 => N167 , I1 => N121 , O => U152_2_INV ) ;
    U154 : X_INV 
      port map ( I => N54 , O => N170 ) ;
    U155 : X_OR2 
      port map ( I0 => N170 , I1 => N64 , O => U155_2_INV ) ;
    U156 : X_OR2 
      port map ( I0 => N63 , I1 => N54 , O => U156_2_INV ) ;
    U158 : X_INV 
      port map ( I => N66 , O => N173 ) ;
    U159 : X_AND2 
      port map ( I0 => N54 , I1 => N173 , O => U159_2_INV ) ;
    U160 : X_OR2 
      port map ( I0 => N65 , I1 => N54 , O => N174 ) ;
    U163 : X_INV 
      port map ( I => N58 , O => N178 ) ;
    U164 : X_AND2 
      port map ( I0 => N54 , I1 => N178 , O => U164_2_INV ) ;
    U165 : X_OR2 
      port map ( I0 => N57 , I1 => N54 , O => N179 ) ;
    U167 : X_INV 
      port map ( I => N54 , O => N181 ) ;
    U168 : X_OR2 
      port map ( I0 => N181 , I1 => N56 , O => U168_2_INV ) ;
    U169 : X_OR2 
      port map ( I0 => N55 , I1 => N54 , O => U169_2_INV ) ;
    U124_1I20 : X_BUF 
      port map ( I => N186 , O => U124_1I20_GTS_TRI ) ;
    U124_1I20_GTS_TRI_0 : X_TRI 
      port map ( I => U124_1I20_GTS_TRI , O => SIG , 
      CTL => U124_1I20_GTS_TRI_2_INV ) ;
    U128_N123_2_0 : X_OR2 
      port map ( I0 => N53 , I1 => N149 , O => U128_2_0 ) ;
    U128_N123 : X_OR2 
      port map ( I0 => U128_2_0 , I1 => N148 , O => U128_N123_2_INV ) ;
    U132_N122_2_0 : X_AND2 
      port map ( I0 => N152 , I1 => N151 , O => U132_2_0 ) ;
    U132_N122 : X_AND2 
      port map ( I0 => U132_2_0 , I1 => N53 , O => N122 ) ;
    U136_N120_2_0 : X_OR2 
      port map ( I0 => N53 , I1 => N155 , O => U136_2_0 ) ;
    U136_N120 : X_OR2 
      port map ( I0 => U136_2_0 , I1 => N154 , O => U136_N120_2_INV ) ;
    U140_N119_2_0 : X_AND2 
      port map ( I0 => N158 , I1 => N157 , O => U140_2_0 ) ;
    U140_N119 : X_AND2 
      port map ( I0 => U140_2_0 , I1 => N53 , O => N119 ) ;
    U147_N163_2_0 : X_OR2 
      port map ( I0 => N162 , I1 => N122 , O => U147_2_0 ) ;
    U147_N163 : X_OR2 
      port map ( I0 => U147_2_0 , I1 => N123 , O => N163 ) ;
    U151_N166_2_0 : X_OR2 
      port map ( I0 => N165 , I1 => N119 , O => U151_2_0 ) ;
    U151_N166 : X_OR2 
      port map ( I0 => U151_2_0 , I1 => N120 , O => N166 ) ;
    U153_N124_2_0 : X_OR2 
      port map ( I0 => N177 , I1 => N52 , O => U153_2_0 ) ;
    U153_N124 : X_OR2 
      port map ( I0 => U153_2_0 , I1 => N176 , O => U153_N124_2_INV ) ;
    U157_N177_2_0 : X_OR2 
      port map ( I0 => N53 , I1 => N172 , O => U157_2_0 ) ;
    U157_N177 : X_OR2 
      port map ( I0 => U157_2_0 , I1 => N171 , O => U157_N177_2_INV ) ;
    U161_N176_2_0 : X_AND2 
      port map ( I0 => N175 , I1 => N174 , O => U161_2_0 ) ;
    U161_N176 : X_AND2 
      port map ( I0 => U161_2_0 , I1 => N53 , O => N176 ) ;
    U162_N121_2_0 : X_OR2 
      port map ( I0 => N184 , I1 => N52 , O => U162_2_0 ) ;
    U162_N121 : X_OR2 
      port map ( I0 => U162_2_0 , I1 => N185 , O => U162_N121_2_INV ) ;
    U166_N185_2_0 : X_AND2 
      port map ( I0 => N180 , I1 => N179 , O => U166_2_0 ) ;
    U166_N185 : X_AND2 
      port map ( I0 => U166_2_0 , I1 => N53 , O => N185 ) ;
    U170_N184_2_0 : X_OR2 
      port map ( I0 => N53 , I1 => N183 , O => U170_2_0 ) ;
    U170_N184 : X_OR2 
      port map ( I0 => U170_2_0 , I1 => N182 , O => U170_N184_2_INV ) ;
    U126_2_INV_1 : X_INV 
      port map ( I => U126_2_INV , O => N148 ) ;
    U127_2_INV_2 : X_INV 
      port map ( I => U127_2_INV , O => N149 ) ;
    U130_2_INV_3 : X_INV 
      port map ( I => U130_2_INV , O => N152 ) ;
    U134_2_INV_4 : X_INV 
      port map ( I => U134_2_INV , O => N154 ) ;
    U135_2_INV_5 : X_INV 
      port map ( I => U135_2_INV , O => N155 ) ;
    U138_2_INV_6 : X_INV 
      port map ( I => U138_2_INV , O => N158 ) ;
    U142_2_INV_7 : X_INV 
      port map ( I => U142_2_INV , O => N161 ) ;
    U144_2_INV_8 : X_INV 
      port map ( I => U144_2_INV , O => N186 ) ;
    U148_2_INV_9 : X_INV 
      port map ( I => U148_2_INV , O => N169 ) ;
    U152_2_INV_10 : X_INV 
      port map ( I => U152_2_INV , O => N168 ) ;
    U155_2_INV_11 : X_INV 
      port map ( I => U155_2_INV , O => N171 ) ;
    U156_2_INV_12 : X_INV 
      port map ( I => U156_2_INV , O => N172 ) ;
    U159_2_INV_13 : X_INV 
      port map ( I => U159_2_INV , O => N175 ) ;
    U164_2_INV_14 : X_INV 
      port map ( I => U164_2_INV , O => N180 ) ;
    U168_2_INV_15 : X_INV 
      port map ( I => U168_2_INV , O => N182 ) ;
    U169_2_INV_16 : X_INV 
      port map ( I => U169_2_INV , O => N183 ) ;
    U128_N123_2_INV_17 : X_INV 
      port map ( I => U128_N123_2_INV , O => N123 ) ;
    U136_N120_2_INV_18 : X_INV 
      port map ( I => U136_N120_2_INV , O => N120 ) ;
    U153_N124_2_INV_19 : X_INV 
      port map ( I => U153_N124_2_INV , O => N124 ) ;
    U157_N177_2_INV_20 : X_INV 
      port map ( I => U157_N177_2_INV , O => N177 ) ;
    U162_N121_2_INV_21 : X_INV 
      port map ( I => U162_N121_2_INV , O => N121 ) ;
    U170_N184_2_INV_22 : X_INV 
      port map ( I => U170_N184_2_INV , O => N184 ) ;
    U124_1I20_GTS_TRI_2_INV_23 : X_INV 
      port map ( I => GTS , O => U124_1I20_GTS_TRI_2_INV ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;