time_sim.v

实用的程序代码

// Xilinx Verilog produced by program ngd2ver, Version M1.4.12
// Date: Tue Jan  6 18:27:20 1998
// Design file: time_sim.nga
// Device: 4005epc84-2
`timescale 1 ns/1 ps
`uselib dir=/home/zeppelin2/tech_apps/m1_4.12/verilog/data libext=.vmd

  module mux_tbuf (A, B, C, D, E, SIG, SEL);
    input A;
    input B;
    input C;
    input D;
    input E;
    output SIG;
    input [4:0] SEL;

    wire n272, n231, SIG_tri_enable197, n228, SIG_tri_enable95, n229, 
    SIG_tri_enable129, n227, SIG_tri_enable, n230, SIG_tri_enable163, 
    \U110/$1I20_GTS_TRI , SIG_tri5_2_INV, SIG_tri2_2_INV, SIG_tri3_2_INV, 
    SIG_tri_2_INV, SIG_tri4_2_INV, \U110/$1I20_GTS_TRI_2_INV ;
    `ifdef GTS_SIGNAL
      wire GTS = `GTS_SIGNAL ;
    `else
      wire GTS ;
    `endif
    initial $sdf_annotate("time_sim.sdf");

    X_TRI SIG_tri5 (.IN (n231), .OUT (n272), .CTL (SIG_tri5_2_INV));
    X_TRI SIG_tri2 (.IN (n228), .OUT (n272), .CTL (SIG_tri2_2_INV));
    X_TRI SIG_tri3 (.IN (n229), .OUT (n272), .CTL (SIG_tri3_2_INV));
    X_TRI SIG_tri (.IN (n227), .OUT (n272), .CTL (SIG_tri_2_INV));
    X_TRI SIG_tri4 (.IN (n230), .OUT (n272), .CTL (SIG_tri4_2_INV));
    X_BUF U100 (.IN (A), .OUT (n227));
    X_BUF U101 (.IN (B), .OUT (n228));
    X_BUF U102 (.IN (C), .OUT (n229));
    X_BUF U103 (.IN (D), .OUT (n230));
    X_BUF U104 (.IN (E), .OUT (n231));
    X_BUF U105 (.IN (SEL[4]), .OUT (SIG_tri_enable197));
    X_BUF U106 (.IN (SEL[3]), .OUT (SIG_tri_enable163));
    X_BUF U107 (.IN (SEL[2]), .OUT (SIG_tri_enable129));
    X_BUF U108 (.IN (SEL[1]), .OUT (SIG_tri_enable95));
    X_BUF U109 (.IN (SEL[0]), .OUT (SIG_tri_enable));
    X_IPAD A_PAD (.PAD (A));
    X_IPAD B_PAD (.PAD (B));
    X_IPAD C_PAD (.PAD (C));
    X_IPAD D_PAD (.PAD (D));
    X_IPAD E_PAD (.PAD (E));
    X_IPAD \SEL<4>_PAD  (.PAD (SEL[4]));
    X_IPAD \SEL<3>_PAD  (.PAD (SEL[3]));
    X_IPAD \SEL<2>_PAD  (.PAD (SEL[2]));
    X_IPAD \SEL<1>_PAD  (.PAD (SEL[1]));
    X_IPAD \SEL<0>_PAD  (.PAD (SEL[0]));
    X_OPAD SIG_PAD (.PAD (SIG));
    X_BUF \U110/$1I20  (.IN (n272), .OUT (\U110/$1I20_GTS_TRI ));
    X_TRI \U110/$1I20_GTS_TRI_29  (.IN (\U110/$1I20_GTS_TRI ), .OUT (SIG), .CTL 
    (\U110/$1I20_GTS_TRI_2_INV ));
    X_INV SIG_tri5_2_INV_30 (.IN (SIG_tri_enable197), .OUT (SIG_tri5_2_INV));
    X_INV SIG_tri2_2_INV_31 (.IN (SIG_tri_enable95), .OUT (SIG_tri2_2_INV));
    X_INV SIG_tri3_2_INV_32 (.IN (SIG_tri_enable129), .OUT (SIG_tri3_2_INV));
    X_INV SIG_tri_2_INV_33 (.IN (SIG_tri_enable), .OUT (SIG_tri_2_INV));
    X_INV SIG_tri4_2_INV_34 (.IN (SIG_tri_enable163), .OUT (SIG_tri4_2_INV));
    X_INV \U110/$1I20_GTS_TRI_2_INV_35  (.IN (GTS), .OUT 
    (\U110/$1I20_GTS_TRI_2_INV ));
    X_PD NGD2VER_PD_29 (.OUT (GTS) );
  endmodule