time_sim.v

实用的程序代码

// Xilinx Verilog produced by program ngd2ver, Version M1.4.12
// Date: Tue Jan  6 18:32:32 1998
// Design file: time_sim.nga
// Device: 4005epc84-2
`timescale 1 ns/1 ps
`uselib dir=/home/zeppelin2/tech_apps/m1_4.12/verilog/data libext=.vmd

  module mux_gate (A, B, C, D, E, SIG, SEL);
    input A;
    input B;
    input C;
    input D;
    input E;
    output SIG;
    input [2:0] SEL;

    wire n63, n64, n65, n66, n67, n68, n69, n70, n119, n109, n108, n93, n94, n97
    , n110, n96, n112, n111, n113, n115, n114, n116, n117, n118, 
    \U67/$1I20_GTS_TRI , \U74/2_0 , \U79/2_0 , \U83/2_0 , U68_2_INV, U69_2_INV, 
    U75_2_INV, U77_2_INV, U81_2_INV, U82_2_INV, \U83/n93_2_INV , 
    \U67/$1I20_GTS_TRI_2_INV ;
    `ifdef GTS_SIGNAL
      wire GTS = `GTS_SIGNAL ;
    `else
      wire GTS ;
    `endif
    initial $sdf_annotate("time_sim.sdf");

    X_BUF U59 (.IN (A), .OUT (n63));
    X_BUF U60 (.IN (B), .OUT (n64));
    X_BUF U61 (.IN (C), .OUT (n65));
    X_BUF U62 (.IN (D), .OUT (n66));
    X_BUF U63 (.IN (E), .OUT (n67));
    X_BUF U64 (.IN (SEL[2]), .OUT (n68));
    X_BUF U65 (.IN (SEL[1]), .OUT (n69));
    X_BUF U66 (.IN (SEL[0]), .OUT (n70));
    X_OR2 U68 (.IN0 (n108), .IN1 (n68), .OUT (U68_2_INV));
    X_OR2 U69 (.IN0 (n93), .IN1 (n94), .OUT (U69_2_INV));
    X_OR2 U70 (.IN0 (n97), .IN1 (n109), .OUT (n119));
    X_INV U71 (.IN (n96), .OUT (n110));
    X_OR2 U72 (.IN0 (n63), .IN1 (n96), .OUT (n112));
    X_OR2 U73 (.IN0 (n110), .IN1 (n67), .OUT (n111));
    X_OR2 U75 (.IN0 (n70), .IN1 (n69), .OUT (U75_2_INV));
    X_INV U76 (.IN (n66), .OUT (n113));
    X_AND2 U77 (.IN0 (n70), .IN1 (n113), .OUT (U77_2_INV));
    X_OR2 U78 (.IN0 (n65), .IN1 (n70), .OUT (n114));
    X_INV U80 (.IN (n70), .OUT (n116));
    X_OR2 U81 (.IN0 (n116), .IN1 (n64), .OUT (U81_2_INV));
    X_OR2 U82 (.IN0 (n63), .IN1 (n70), .OUT (U82_2_INV));
    X_IPAD A_PAD (.PAD (A));
    X_IPAD B_PAD (.PAD (B));
    X_IPAD C_PAD (.PAD (C));
    X_IPAD D_PAD (.PAD (D));
    X_IPAD E_PAD (.PAD (E));
    X_IPAD \SEL<2>_PAD  (.PAD (SEL[2]));
    X_IPAD \SEL<1>_PAD  (.PAD (SEL[1]));
    X_IPAD \SEL<0>_PAD  (.PAD (SEL[0]));
    X_OPAD SIG_PAD (.PAD (SIG));
    X_BUF \U67/$1I20  (.IN (n119), .OUT (\U67/$1I20_GTS_TRI ));
    X_TRI \U67/$1I20_GTS_TRI_47  (.IN (\U67/$1I20_GTS_TRI ), .OUT (SIG), .CTL 
    (\U67/$1I20_GTS_TRI_2_INV ));
    X_AND2 \U74/n97/2_0  (.IN0 (n112), .IN1 (n111), .OUT (\U74/2_0 ));
    X_AND2 \U74/n97  (.IN0 (\U74/2_0 ), .IN1 (n68), .OUT (n97));
    X_AND2 \U79/n94/2_0  (.IN0 (n115), .IN1 (n114), .OUT (\U79/2_0 ));
    X_AND2 \U79/n94  (.IN0 (\U79/2_0 ), .IN1 (n69), .OUT (n94));
    X_OR2 \U83/n93/2_0  (.IN0 (n69), .IN1 (n118), .OUT (\U83/2_0 ));
    X_OR2 \U83/n93  (.IN0 (\U83/2_0 ), .IN1 (n117), .OUT (\U83/n93_2_INV ));
    X_INV U68_2_INV_48 (.IN (U68_2_INV), .OUT (n109));
    X_INV U69_2_INV_49 (.IN (U69_2_INV), .OUT (n108));
    X_INV U75_2_INV_50 (.IN (U75_2_INV), .OUT (n96));
    X_INV U77_2_INV_51 (.IN (U77_2_INV), .OUT (n115));
    X_INV U81_2_INV_52 (.IN (U81_2_INV), .OUT (n117));
    X_INV U82_2_INV_53 (.IN (U82_2_INV), .OUT (n118));
    X_INV \U83/n93_2_INV_54  (.IN (\U83/n93_2_INV ), .OUT (n93));
    X_INV \U67/$1I20_GTS_TRI_2_INV_55  (.IN (GTS), .OUT 
    (\U67/$1I20_GTS_TRI_2_INV ));
    X_PD NGD2VER_PD_45 (.OUT (GTS) );
  endmodule