time_sim.tv

实用的程序代码

// VERILOG TestFixture Template produced by ngd2ver M1.4.12
// Design file: time_sim.nga
// Date:Tue Jan  6 18:30:01 1998

// ATTENTION: This file was created by NGD2VER and may therefore be overwritten
// by subsequent runs of NGD2VER. Xilinx recommends that you copy this file to
// a new name, or 'paste' this text into another file, to avoid accidental loss
// of data.

`timescale 1 ns/1 ps

module test;
  wire SIG;
  reg A;
  reg B;
  reg C;
  reg D;
  reg E;
  reg F;
  reg G;
  reg H;
  reg I;
  reg J;
  reg K;
  reg L;
  reg M;
  reg N;
  reg O;
  reg P;
  reg [3:0] SEL;

  reg GTS;
  `define GTS_SIGNAL test.GTS

  mux_gate16 uut ( .SIG (SIG) , .A (A) , .B (B) , .C (C) 
, .D (D) , .E (E) , .F (F) , .G (G) , .H (H) 
, .I (I) , .J (J) , .K (K) , .L (L) , .M (M) 
, .N (N) , .O (O) , .P (P) , .SEL (SEL) );

  initial begin
    $timeformat(-9,3,"ns",12);
    $shm_open("time_sim.shm");
    $shm_probe("AS");
  end

  initial begin
    $display("           T SABCDEFGHIJKLMNOPS");
    $display("           i I                E");
    $display("           m G                L");
    $display("           e                  [");
    $display("                              3");
    $display("                              :");
    $display("                              0");
    $display("                              ]");
    $monitor("%t",$realtime,, SIG, A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, "%h", SEL );
  end

  initial begin
      `GTS_SIGNAL = 0;
    #100
      A = 0 ;
      B = 0 ;
      C = 0 ;
      D = 0 ;
      E = 0 ;
      F = 0 ;
      G = 0 ;
      H = 0 ;
      I = 0 ;
      J = 0 ;
      K = 0 ;
      L = 0 ;
      M = 0 ;
      N = 0 ;
      O = 0 ;
      P = 0 ;
      SEL = 0 ;
    #1000 $stop;
    // #1000 $finish;
  end

endmodule