tim_sim.tv

实用的程序代码

// VERILOG TestFixture Template produced by ngd2ver M1.3.7
// Design file: tim_sim.nga
// Date:Tue Oct 14 17:48:48 1997

// ATTENTION: This file was created by NGD2VER and may therefore be overwritten
// by subsequent runs of NGD2VER. Xilinx recommends that you copy this file to
// a new name, or 'paste' this text into another file, to avoid accidental loss
// of data.

`timescale 1 ns/1 ps

module test;
  reg LOAD;
  reg IN2;
  reg IN1;
  wire DOUT;
  reg DATA;
  reg CLK;

  reg GSR;
  `define GSR_SIGNAL test.GSR

  reg GTS;
  `define GTS_SIGNAL test.GTS

  clock_enable uut ( .LOAD (LOAD) , .IN2 (IN2) , .IN1 (IN1) , .DOUT (DOUT) 
, .DATA (DATA) , .CLK (CLK) );

  initial begin
    $timeformat(-9,3,"ns",12);
    $shm_open("tim_sim.shm");
    $shm_probe("AS");
  end

  initial begin
    $display("           T LIIDDC");
    $display("           i ONNOAL");
    $display("           m A21UTK");
    $display("           e D  TA ");
    $monitor("%t",$realtime,, LOAD, IN2, IN1, DOUT, DATA, CLK );
  end

  initial begin
      `GSR_SIGNAL = 1;
      `GTS_SIGNAL = 0;
    #100
      `GSR_SIGNAL = 0;
      LOAD = 1 ;
      IN2 = 1 ;
      IN1 = 1 ;
      DATA = 0 ;
      CLK = 0 ;
    #100
      CLK = 1 ;
    #10
      DATA = 1 ;
    #10
      DATA = 0 ;
    #10
      CLK = 0 ;
    #10
      DATA = 1 ;
    #10
      DATA = 0 ;
    #10
      CLK = 1 ;
    #10
      DATA = 1 ;
    #20
      CLK = 0 ;
    #30
      CLK = 1 ;
    #10
      DATA = 0 ;
    #20
      CLK = 0 ;
    #30
      CLK = 1 ;
      DATA = 1 ;
    #30
      CLK = 0 ;
    #30
      CLK = 1 ;
   
    #60 $stop;
    // #1000 $finish;
  end

endmodule