📄 tim_sim.v
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// Xilinx Verilog produced by program ngd2ver, Version M1.3.7// Date: Tue Oct 14 17:48:48 1997// Design file: tim_sim.nga// Device: 4005epc84-2`timescale 1 ns/1 ps`uselib dir=/home/zeppelin2/tech_apps/m1_3.7/verilog/data libext=.vmd module clock_enable (LOAD, IN2, IN1, DOUT, DATA, CLK); input LOAD; input IN2; input IN1; output DOUT; input DATA; input CLK; wire n74, n75, n76, n77, n78, n101, ENABLE, n100, DOUT_reg_GSR_OR, \U45/$1I20_GTS_TRI , \U43/clkio_bufsig , \U46/2_0 , \U45/$1I20_GTS_TRI_2_INV , GND; `ifdef GSR_SIGNAL wire GSR = `GSR_SIGNAL ; `else wire GSR ; `endif `ifdef GTS_SIGNAL wire GTS = `GTS_SIGNAL ; `else wire GTS ; `endif initial $sdf_annotate("tim_sim.sdf"); X_BUF U40 (.IN (IN1), .OUT (n74)); X_BUF U41 (.IN (IN2), .OUT (n75)); X_BUF U42 (.IN (DATA), .OUT (n76)); X_BUF U44 (.IN (LOAD), .OUT (n78)); X_FF DOUT_reg (.IN (n76), .CLK (n77), .CE (ENABLE), .SET (GND), .RST (DOUT_reg_GSR_OR), .OUT (n101)); X_IPAD IN1_PAD (.PAD (IN1)); X_IPAD IN2_PAD (.PAD (IN2)); X_IPAD DATA_PAD (.PAD (DATA)); X_IPAD CLK_PAD (.PAD (CLK)); X_IPAD LOAD_PAD (.PAD (LOAD)); X_OPAD DOUT_PAD (.PAD (DOUT)); X_ZERO n100_ZERO (.OUT (n100)); X_OR2 DOUT_reg_GSR_OR_22 (.IN0 (n100), .IN1 (GSR), .OUT (DOUT_reg_GSR_OR)); X_BUF \U45/$1I20 (.IN (n101), .OUT (\U45/$1I20_GTS_TRI )); X_TRI \U45/$1I20_GTS_TRI_23 (.IN (\U45/$1I20_GTS_TRI ), .OUT (DOUT), .CTL (\U45/$1I20_GTS_TRI_2_INV )); X_CKBUF \U43/clkbuf (.IN (\U43/clkio_bufsig ), .OUT (n77)); X_BUF \U43/clkio_buf (.IN (CLK), .OUT (\U43/clkio_bufsig )); X_AND2 \U46/ENABLE/2_0 (.IN0 (n74), .IN1 (n75), .OUT (\U46/2_0 )); X_AND2 \U46/ENABLE (.IN0 (\U46/2_0 ), .IN1 (n78), .OUT (ENABLE)); X_INV \U45/$1I20_GTS_TRI_2_INV_24 (.IN (GTS), .OUT (\U45/$1I20_GTS_TRI_2_INV )); X_ZERO GND_25 (.OUT (GND)); X_PD NGD2VER_PD_20 (.OUT (GSR) ); X_PD NGD2VER_PD_21 (.OUT (GTS) ); endmodule
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