time_sim.vhd

实用的程序代码

    ADD_41_PLUS_PLUS_U6_S0_1_XOR2_SUM_1_0 : X_XOR2 
      port map ( I0 => ADD_41_PLUS_PLUS_U6_S0_1_CO_0 , 
      I1 => ADD_41_PLUS_PLUS_U6_S0_1_MUX_SEL_1_0 , O => ARG58(0) ) ;
    ADD_41_PLUS_PLUS_U6_S0_1_XOR1_MUX_SEL_1_0 : X_XOR2 
      port map ( I0 => N213 , 
      I1 => ADD_41_PLUS_PLUS_U6_S0_1_XOR1_MUX_SEL_1_0_1_INV , 
      O => ADD_41_PLUS_PLUS_U6_S0_1_MUX_SEL_1_0 ) ;
    ADD_41_PLUS_PLUS_U6_GND_ZERO : X_ZERO 
      port map ( O => ADD_41_PLUS_PLUS_U6_GND ) ;
    ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_AND0_16 : X_AND2 
      port map ( I0 => N211 , 
      I1 => ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_AND0_1_INV , 
      O => ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_AND0 ) ;
    ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_AND1_17 : X_AND2 
      port map ( I0 => ADD_41_PLUS_PLUS_U6_S0_1_CO_2 , 
      I1 => ADD_41_PLUS_PLUS_U6_S0_1_MUX_SEL_1_2 , 
      O => ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_AND1 ) ;
    ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_OR : X_OR2 
      port map ( I0 => ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_AND0 , 
      I1 => ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_AND1 , 
      O => ADD_41_PLUS_PLUS_U6_S0_1_CO_3 ) ;
    ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_AND0_18 : X_AND2 
      port map ( I0 => N212 , 
      I1 => ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_AND0_1_INV , 
      O => ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_AND0 ) ;
    ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_AND1_19 : X_AND2 
      port map ( I0 => ADD_41_PLUS_PLUS_U6_S0_1_CO_1 , 
      I1 => ADD_41_PLUS_PLUS_U6_S0_1_MUX_SEL_1_1 , 
      O => ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_AND1 ) ;
    ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_OR : X_OR2 
      port map ( I0 => ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_AND0 , 
      I1 => ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_AND1 , 
      O => ADD_41_PLUS_PLUS_U6_S0_1_CO_2 ) ;
    ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_AND0_20 : X_AND2 
      port map ( I0 => N213 , 
      I1 => ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_AND0_1_INV , 
      O => ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_AND0 ) ;
    ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_AND1_21 : X_AND2 
      port map ( I0 => ADD_41_PLUS_PLUS_U6_S0_1_CO_0 , 
      I1 => ADD_41_PLUS_PLUS_U6_S0_1_MUX_SEL_1_0 , 
      O => ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_AND1 ) ;
    ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_OR : X_OR2 
      port map ( I0 => ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_AND0 , 
      I1 => ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_AND1 , 
      O => ADD_41_PLUS_PLUS_U6_S0_1_CO_1 ) ;
    ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_AND0_22 : X_AND2 
      port map ( I0 => ADD_41_PLUS_PLUS_N19 , 
      I1 => ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_AND0_1_INV , 
      O => ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_AND0 ) ;
    ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_AND1_23 : X_AND2 
      port map ( I0 => VCC , I1 => ADD_41_PLUS_PLUS_U6_GND , 
      O => ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_AND1 ) ;
    ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_OR : X_OR2 
      port map ( I0 => ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_AND0 , 
      I1 => ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_AND1 , 
      O => ADD_41_PLUS_PLUS_U6_S0_1_CO_0 ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_XOR8_SUM_1_3 : X_XOR2 
      port map ( I0 => SUB_50_MINUS_MINUS_U6_S0_1_CO_3 , 
      I1 => SUB_50_MINUS_MINUS_U6_S0_1_MUX_SEL_1_3 , O => ARG139(3) ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_XOR7_MUX_SEL_1_3 : X_XOR2 
      port map ( I0 => N214 , 
      I1 => SUB_50_MINUS_MINUS_U6_S0_1_XOR7_MUX_SEL_1_3_1_INV , 
      O => SUB_50_MINUS_MINUS_U6_S0_1_MUX_SEL_1_3 ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_XOR6_SUM_1_2 : X_XOR2 
      port map ( I0 => SUB_50_MINUS_MINUS_U6_S0_1_CO_2 , 
      I1 => SUB_50_MINUS_MINUS_U6_S0_1_MUX_SEL_1_2 , O => ARG139(2) ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_XOR5_MUX_SEL_1_2 : X_XOR2 
      port map ( I0 => N215 , 
      I1 => SUB_50_MINUS_MINUS_U6_S0_1_XOR5_MUX_SEL_1_2_1_INV , 
      O => SUB_50_MINUS_MINUS_U6_S0_1_MUX_SEL_1_2 ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_XOR4_SUM_1_1 : X_XOR2 
      port map ( I0 => SUB_50_MINUS_MINUS_U6_S0_1_CO_1 , 
      I1 => SUB_50_MINUS_MINUS_U6_S0_1_MUX_SEL_1_1 , O => ARG139(1) ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_XOR3_MUX_SEL_1_1 : X_XOR2 
      port map ( I0 => N216 , 
      I1 => SUB_50_MINUS_MINUS_U6_S0_1_XOR3_MUX_SEL_1_1_1_INV , 
      O => SUB_50_MINUS_MINUS_U6_S0_1_MUX_SEL_1_1 ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_XOR2_SUM_1_0 : X_XOR2 
      port map ( I0 => SUB_50_MINUS_MINUS_U6_S0_1_CO_0 , 
      I1 => SUB_50_MINUS_MINUS_U6_S0_1_MUX_SEL_1_0 , O => ARG139(0) ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_XOR1_MUX_SEL_1_0 : X_XOR2 
      port map ( I0 => N217 , 
      I1 => SUB_50_MINUS_MINUS_U6_S0_1_XOR1_MUX_SEL_1_0_1_INV , 
      O => SUB_50_MINUS_MINUS_U6_S0_1_MUX_SEL_1_0 ) ;
    SUB_50_MINUS_MINUS_U6_GND_ZERO : X_ZERO 
      port map ( O => SUB_50_MINUS_MINUS_U6_GND ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_2_AND0_24 : X_AND2 
      port map ( I0 => N215 , 
      I1 => SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_2_AND0_1_INV , 
      O => SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_2_AND0 ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_2_AND1_25 : X_AND2 
      port map ( I0 => SUB_50_MINUS_MINUS_U6_S0_1_CO_2 , 
      I1 => SUB_50_MINUS_MINUS_U6_S0_1_MUX_SEL_1_2 , 
      O => SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_2_AND1 ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_2_OR : X_OR2 
      port map ( I0 => SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_2_AND0 , 
      I1 => SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_2_AND1 , 
      O => SUB_50_MINUS_MINUS_U6_S0_1_CO_3 ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_1_AND0_26 : X_AND2 
      port map ( I0 => N216 , 
      I1 => SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_1_AND0_1_INV , 
      O => SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_1_AND0 ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_1_AND1_27 : X_AND2 
      port map ( I0 => SUB_50_MINUS_MINUS_U6_S0_1_CO_1 , 
      I1 => SUB_50_MINUS_MINUS_U6_S0_1_MUX_SEL_1_1 , 
      O => SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_1_AND1 ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_1_OR : X_OR2 
      port map ( I0 => SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_1_AND0 , 
      I1 => SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_1_AND1 , 
      O => SUB_50_MINUS_MINUS_U6_S0_1_CO_2 ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_0_AND0_28 : X_AND2 
      port map ( I0 => N217 , 
      I1 => SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_0_AND0_1_INV , 
      O => SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_0_AND0 ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_0_AND1_29 : X_AND2 
      port map ( I0 => SUB_50_MINUS_MINUS_U6_S0_1_CO_0 , 
      I1 => SUB_50_MINUS_MINUS_U6_S0_1_MUX_SEL_1_0 , 
      O => SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_0_AND1 ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_0_OR : X_OR2 
      port map ( I0 => SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_0_AND0 , 
      I1 => SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_0_AND1 , 
      O => SUB_50_MINUS_MINUS_U6_S0_1_CO_1 ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_0_3_AND0_30 : X_AND2 
      port map ( I0 => SUB_50_MINUS_MINUS_N20 , 
      I1 => SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_0_3_AND0_1_INV , 
      O => SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_0_3_AND0 ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_0_3_AND1_31 : X_AND2 
      port map ( I0 => VCC , I1 => SUB_50_MINUS_MINUS_U6_GND , 
      O => SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_0_3_AND1 ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_0_3_OR : X_OR2 
      port map ( I0 => SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_0_3_AND0 , 
      I1 => SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_0_3_AND1 , 
      O => SUB_50_MINUS_MINUS_U6_S0_1_CO_0 ) ;
    U58_CLKBUF : X_CKBUF 
      port map ( I => U58_CLKIO_BUFSIG , O => N188 ) ;
    U58_CLKIO_BUF : X_BUF 
      port map ( I => CLOCK , O => U58_CLKIO_BUFSIG ) ;
    ADD_41_PLUS_PLUS_U6_S0_1_XOR7_MUX_SEL_1_3_1_INV_32 : X_INV 
      port map ( I => ADD_41_PLUS_PLUS_N19 , 
      O => ADD_41_PLUS_PLUS_U6_S0_1_XOR7_MUX_SEL_1_3_1_INV ) ;
    ADD_41_PLUS_PLUS_U6_S0_1_XOR5_MUX_SEL_1_2_1_INV_33 : X_INV 
      port map ( I => ADD_41_PLUS_PLUS_N19 , 
      O => ADD_41_PLUS_PLUS_U6_S0_1_XOR5_MUX_SEL_1_2_1_INV ) ;
    ADD_41_PLUS_PLUS_U6_S0_1_XOR3_MUX_SEL_1_1_1_INV_34 : X_INV 
      port map ( I => ADD_41_PLUS_PLUS_N19 , 
      O => ADD_41_PLUS_PLUS_U6_S0_1_XOR3_MUX_SEL_1_1_1_INV ) ;
    ADD_41_PLUS_PLUS_U6_S0_1_XOR1_MUX_SEL_1_0_1_INV_35 : X_INV 
      port map ( I => ADD_41_PLUS_PLUS_N19 , 
      O => ADD_41_PLUS_PLUS_U6_S0_1_XOR1_MUX_SEL_1_0_1_INV ) ;
    ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_AND0_1_INV_36 : X_INV 
      port map ( I => ADD_41_PLUS_PLUS_U6_S0_1_MUX_SEL_1_2 , 
      O => ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_AND0_1_INV ) ;
    ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_AND0_1_INV_37 : X_INV 
      port map ( I => ADD_41_PLUS_PLUS_U6_S0_1_MUX_SEL_1_1 , 
      O => ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_AND0_1_INV ) ;
    ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_AND0_1_INV_38 : X_INV 
      port map ( I => ADD_41_PLUS_PLUS_U6_S0_1_MUX_SEL_1_0 , 
      O => ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_AND0_1_INV ) ;
    ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_AND0_1_INV_39 : X_INV 
      port map ( I => ADD_41_PLUS_PLUS_U6_GND , 
      O => ADD_41_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_AND0_1_INV ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_XOR7_MUX_SEL_1_3_1_INV_40 : X_INV 
      port map ( I => SUB_50_MINUS_MINUS_N20 , 
      O => SUB_50_MINUS_MINUS_U6_S0_1_XOR7_MUX_SEL_1_3_1_INV ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_XOR5_MUX_SEL_1_2_1_INV_41 : X_INV 
      port map ( I => SUB_50_MINUS_MINUS_N20 , 
      O => SUB_50_MINUS_MINUS_U6_S0_1_XOR5_MUX_SEL_1_2_1_INV ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_XOR3_MUX_SEL_1_1_1_INV_42 : X_INV 
      port map ( I => SUB_50_MINUS_MINUS_N20 , 
      O => SUB_50_MINUS_MINUS_U6_S0_1_XOR3_MUX_SEL_1_1_1_INV ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_XOR1_MUX_SEL_1_0_1_INV_43 : X_INV 
      port map ( I => SUB_50_MINUS_MINUS_N20 , 
      O => SUB_50_MINUS_MINUS_U6_S0_1_XOR1_MUX_SEL_1_0_1_INV ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_2_AND0_1_INV_44 : X_INV 
      port map ( I => SUB_50_MINUS_MINUS_U6_S0_1_MUX_SEL_1_2 , 
      O => SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_2_AND0_1_INV ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_1_AND0_1_INV_45 : X_INV 
      port map ( I => SUB_50_MINUS_MINUS_U6_S0_1_MUX_SEL_1_1 , 
      O => SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_1_AND0_1_INV ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_0_AND0_1_INV_46 : X_INV 
      port map ( I => SUB_50_MINUS_MINUS_U6_S0_1_MUX_SEL_1_0 , 
      O => SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_1_0_AND0_1_INV ) ;
    SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_0_3_AND0_1_INV_47 : X_INV 
      port map ( I => SUB_50_MINUS_MINUS_U6_GND , 
      O => SUB_50_MINUS_MINUS_U6_S0_1_CY_MUX_0_3_AND0_1_INV ) ;
    U49_1I20_GTS_TRI_2_INV_48 : X_INV 
      port map ( I => GTS , O => U49_1I20_GTS_TRI_2_INV ) ;
    U50_1I20_GTS_TRI_2_INV_49 : X_INV 
      port map ( I => GTS , O => U50_1I20_GTS_TRI_2_INV ) ;
    U51_1I20_GTS_TRI_2_INV_50 : X_INV 
      port map ( I => GTS , O => U51_1I20_GTS_TRI_2_INV ) ;
    U52_1I20_GTS_TRI_2_INV_51 : X_INV 
      port map ( I => GTS , O => U52_1I20_GTS_TRI_2_INV ) ;
    U53_1I20_GTS_TRI_2_INV_52 : X_INV 
      port map ( I => GTS , O => U53_1I20_GTS_TRI_2_INV ) ;
    U54_1I20_GTS_TRI_2_INV_53 : X_INV 
      port map ( I => GTS , O => U54_1I20_GTS_TRI_2_INV ) ;
    U55_1I20_GTS_TRI_2_INV_54 : X_INV 
      port map ( I => GTS , O => U55_1I20_GTS_TRI_2_INV ) ;
    U56_1I20_GTS_TRI_2_INV_55 : X_INV 
      port map ( I => GTS , O => U56_1I20_GTS_TRI_2_INV ) ;
    VCC_56 : X_ONE 
      port map ( O => VCC ) ;
    GND_57 : X_ZERO 
      port map ( O => GND ) ;
end STRUCTURE ;