no_gr.twr

来自「实用的程序代码」· TWR 代码 · 共 59 行

--------------------------------------------------------------------------------
Xilinx TRACE, Version M1.4.12
Copyright (c) 1995-1997 Xilinx, Inc.  All rights reserved.

Design file:              no_gr.ncd
Physical constraint file: no_gr.pcf
Device,speed:             xc5202,-4 (1.35__5200.5_5202.13)
Report level:             summary report
--------------------------------------------------------------------------------

WARNING:bastw:172 - No timing constraints found, doing advanced analysis with
   offsets.

================================================================================
Timing constraint: Default period analysis for net n188
 28 items analyzed, 0 timing errors detected.
 Minimum period is  19.146ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: Default OFFSET IN BEFORE analysis for clock "n188"
 8 items analyzed, 0 timing errors detected.
 Minimum allowable offset is   3.101ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: Default OFFSET OUT AFTER analysis for clock "n188"
 8 items analyzed, 0 timing errors detected.
 Maximum allowable offset is  17.177ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: Default path analysis
 16 items analyzed, 0 timing errors detected.
 Maximum delay is  13.261ns.
--------------------------------------------------------------------------------


All constraints were met.


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 52 paths, 0 nets, and 64 connections (94.1% coverage)

Design statistics:
   Minimum period:  19.146ns (Maximum frequency:  52.230MHz)
   Maximum combinational path delay:  13.261ns
   Minimum input arrival time before clock:   3.101ns
   Maximum output required time before clock:  17.177ns


Analysis completed Wed Jan  7 10:01:40 1998
--------------------------------------------------------------------------------