time_sim.v

实用的程序代码

    X_XOR2 \add_26/u6/S0_1/XOR4_SUM_1_1  (.IN0 (\add_26/u6/S0_1/CO_1 ), .IN1 
    (\add_26/u6/S0_1/MUX_SEL_1_1 ), .OUT (UPCNT37[1]));
    X_XOR2 \add_26/u6/S0_1/XOR3_MUX_SEL_1_1  (.IN0 (n123), .IN1 
    (\add_26/u6/S0_1/XOR3_MUX_SEL_1_1_1_INV ), .OUT 
    (\add_26/u6/S0_1/MUX_SEL_1_1 ));
    X_XOR2 \add_26/u6/S0_1/XOR2_SUM_1_0  (.IN0 (\add_26/u6/S0_1/CO_0 ), .IN1 
    (\add_26/u6/S0_1/MUX_SEL_1_0 ), .OUT (UPCNT37[0]));
    X_XOR2 \add_26/u6/S0_1/XOR1_MUX_SEL_1_0  (.IN0 (n124), .IN1 
    (\add_26/u6/S0_1/XOR1_MUX_SEL_1_0_1_INV ), .OUT 
    (\add_26/u6/S0_1/MUX_SEL_1_0 ));
    X_ZERO \add_26/u6/GND_ZERO  (.OUT (\add_26/u6/GND ));
    X_AND2 \add_26/u6/S0_1/CY_MUX_1_2/AND0_82  (.IN0 (n122), .IN1 
    (\add_26/u6/S0_1/CY_MUX_1_2/AND0_1_INV ), .OUT 
    (\add_26/u6/S0_1/CY_MUX_1_2/AND0 ));
    X_AND2 \add_26/u6/S0_1/CY_MUX_1_2/AND1_83  (.IN0 (\add_26/u6/S0_1/CO_2 ), 
    .IN1 (\add_26/u6/S0_1/MUX_SEL_1_2 ), .OUT (\add_26/u6/S0_1/CY_MUX_1_2/AND1 )
    );
    X_OR2 \add_26/u6/S0_1/CY_MUX_1_2/OR  (.IN0 
    (\add_26/u6/S0_1/CY_MUX_1_2/AND0 ), .IN1 (\add_26/u6/S0_1/CY_MUX_1_2/AND1 )
    , .OUT (\add_26/u6/S0_1/CO_3 ));
    X_AND2 \add_26/u6/S0_1/CY_MUX_1_1/AND0_85  (.IN0 (n123), .IN1 
    (\add_26/u6/S0_1/CY_MUX_1_1/AND0_1_INV ), .OUT 
    (\add_26/u6/S0_1/CY_MUX_1_1/AND0 ));
    X_AND2 \add_26/u6/S0_1/CY_MUX_1_1/AND1_86  (.IN0 (\add_26/u6/S0_1/CO_1 ), 
    .IN1 (\add_26/u6/S0_1/MUX_SEL_1_1 ), .OUT (\add_26/u6/S0_1/CY_MUX_1_1/AND1 )
    );
    X_OR2 \add_26/u6/S0_1/CY_MUX_1_1/OR  (.IN0 
    (\add_26/u6/S0_1/CY_MUX_1_1/AND0 ), .IN1 (\add_26/u6/S0_1/CY_MUX_1_1/AND1 )
    , .OUT (\add_26/u6/S0_1/CO_2 ));
    X_AND2 \add_26/u6/S0_1/CY_MUX_1_0/AND0_88  (.IN0 (n124), .IN1 
    (\add_26/u6/S0_1/CY_MUX_1_0/AND0_1_INV ), .OUT 
    (\add_26/u6/S0_1/CY_MUX_1_0/AND0 ));
    X_AND2 \add_26/u6/S0_1/CY_MUX_1_0/AND1_89  (.IN0 (\add_26/u6/S0_1/CO_0 ), 
    .IN1 (\add_26/u6/S0_1/MUX_SEL_1_0 ), .OUT (\add_26/u6/S0_1/CY_MUX_1_0/AND1 )
    );
    X_OR2 \add_26/u6/S0_1/CY_MUX_1_0/OR  (.IN0 
    (\add_26/u6/S0_1/CY_MUX_1_0/AND0 ), .IN1 (\add_26/u6/S0_1/CY_MUX_1_0/AND1 )
    , .OUT (\add_26/u6/S0_1/CO_1 ));
    X_AND2 \add_26/u6/S0_1/CY_MUX_0_3/AND0_91  (.IN0 (\add_26/n19 ), .IN1 
    (\add_26/u6/S0_1/CY_MUX_0_3/AND0_1_INV ), .OUT 
    (\add_26/u6/S0_1/CY_MUX_0_3/AND0 ));
    X_AND2 \add_26/u6/S0_1/CY_MUX_0_3/AND1_92  (.IN0 (VCC), .IN1 
    (\add_26/u6/GND ), .OUT (\add_26/u6/S0_1/CY_MUX_0_3/AND1 ));
    X_OR2 \add_26/u6/S0_1/CY_MUX_0_3/OR  (.IN0 
    (\add_26/u6/S0_1/CY_MUX_0_3/AND0 ), .IN1 (\add_26/u6/S0_1/CY_MUX_0_3/AND1 )
    , .OUT (\add_26/u6/S0_1/CO_0 ));
    X_XOR2 \sub_27/u6/S0_1/XOR8_SUM_1_3  (.IN0 (\sub_27/u6/S0_1/CO_3 ), .IN1 
    (\sub_27/u6/S0_1/MUX_SEL_1_3 ), .OUT (DNCNT44[3]));
    X_XOR2 \sub_27/u6/S0_1/XOR7_MUX_SEL_1_3  (.IN0 (n125), .IN1 
    (\sub_27/u6/S0_1/XOR7_MUX_SEL_1_3_1_INV ), .OUT 
    (\sub_27/u6/S0_1/MUX_SEL_1_3 ));
    X_XOR2 \sub_27/u6/S0_1/XOR6_SUM_1_2  (.IN0 (\sub_27/u6/S0_1/CO_2 ), .IN1 
    (\sub_27/u6/S0_1/MUX_SEL_1_2 ), .OUT (DNCNT44[2]));
    X_XOR2 \sub_27/u6/S0_1/XOR5_MUX_SEL_1_2  (.IN0 (n126), .IN1 
    (\sub_27/u6/S0_1/XOR5_MUX_SEL_1_2_1_INV ), .OUT 
    (\sub_27/u6/S0_1/MUX_SEL_1_2 ));
    X_XOR2 \sub_27/u6/S0_1/XOR4_SUM_1_1  (.IN0 (\sub_27/u6/S0_1/CO_1 ), .IN1 
    (\sub_27/u6/S0_1/MUX_SEL_1_1 ), .OUT (DNCNT44[1]));
    X_XOR2 \sub_27/u6/S0_1/XOR3_MUX_SEL_1_1  (.IN0 (n127), .IN1 
    (\sub_27/u6/S0_1/XOR3_MUX_SEL_1_1_1_INV ), .OUT 
    (\sub_27/u6/S0_1/MUX_SEL_1_1 ));
    X_XOR2 \sub_27/u6/S0_1/XOR2_SUM_1_0  (.IN0 (\sub_27/u6/S0_1/CO_0 ), .IN1 
    (\sub_27/u6/S0_1/MUX_SEL_1_0 ), .OUT (DNCNT44[0]));
    X_XOR2 \sub_27/u6/S0_1/XOR1_MUX_SEL_1_0  (.IN0 (n128), .IN1 
    (\sub_27/u6/S0_1/XOR1_MUX_SEL_1_0_1_INV ), .OUT 
    (\sub_27/u6/S0_1/MUX_SEL_1_0 ));
    X_ZERO \sub_27/u6/GND_ZERO  (.OUT (\sub_27/u6/GND ));
    X_AND2 \sub_27/u6/S0_1/CY_MUX_1_2/AND0_130  (.IN0 (n126), .IN1 
    (\sub_27/u6/S0_1/CY_MUX_1_2/AND0_1_INV ), .OUT 
    (\sub_27/u6/S0_1/CY_MUX_1_2/AND0 ));
    X_AND2 \sub_27/u6/S0_1/CY_MUX_1_2/AND1_131  (.IN0 (\sub_27/u6/S0_1/CO_2 ), 
    .IN1 (\sub_27/u6/S0_1/MUX_SEL_1_2 ), .OUT (\sub_27/u6/S0_1/CY_MUX_1_2/AND1 )
    );
    X_OR2 \sub_27/u6/S0_1/CY_MUX_1_2/OR  (.IN0 
    (\sub_27/u6/S0_1/CY_MUX_1_2/AND0 ), .IN1 (\sub_27/u6/S0_1/CY_MUX_1_2/AND1 )
    , .OUT (\sub_27/u6/S0_1/CO_3 ));
    X_AND2 \sub_27/u6/S0_1/CY_MUX_1_1/AND0_133  (.IN0 (n127), .IN1 
    (\sub_27/u6/S0_1/CY_MUX_1_1/AND0_1_INV ), .OUT 
    (\sub_27/u6/S0_1/CY_MUX_1_1/AND0 ));
    X_AND2 \sub_27/u6/S0_1/CY_MUX_1_1/AND1_134  (.IN0 (\sub_27/u6/S0_1/CO_1 ), 
    .IN1 (\sub_27/u6/S0_1/MUX_SEL_1_1 ), .OUT (\sub_27/u6/S0_1/CY_MUX_1_1/AND1 )
    );
    X_OR2 \sub_27/u6/S0_1/CY_MUX_1_1/OR  (.IN0 
    (\sub_27/u6/S0_1/CY_MUX_1_1/AND0 ), .IN1 (\sub_27/u6/S0_1/CY_MUX_1_1/AND1 )
    , .OUT (\sub_27/u6/S0_1/CO_2 ));
    X_AND2 \sub_27/u6/S0_1/CY_MUX_1_0/AND0_136  (.IN0 (n128), .IN1 
    (\sub_27/u6/S0_1/CY_MUX_1_0/AND0_1_INV ), .OUT 
    (\sub_27/u6/S0_1/CY_MUX_1_0/AND0 ));
    X_AND2 \sub_27/u6/S0_1/CY_MUX_1_0/AND1_137  (.IN0 (\sub_27/u6/S0_1/CO_0 ), 
    .IN1 (\sub_27/u6/S0_1/MUX_SEL_1_0 ), .OUT (\sub_27/u6/S0_1/CY_MUX_1_0/AND1 )
    );
    X_OR2 \sub_27/u6/S0_1/CY_MUX_1_0/OR  (.IN0 
    (\sub_27/u6/S0_1/CY_MUX_1_0/AND0 ), .IN1 (\sub_27/u6/S0_1/CY_MUX_1_0/AND1 )
    , .OUT (\sub_27/u6/S0_1/CO_1 ));
    X_AND2 \sub_27/u6/S0_1/CY_MUX_0_3/AND0_139  (.IN0 (\sub_27/n20 ), .IN1 
    (\sub_27/u6/S0_1/CY_MUX_0_3/AND0_1_INV ), .OUT 
    (\sub_27/u6/S0_1/CY_MUX_0_3/AND0 ));
    X_AND2 \sub_27/u6/S0_1/CY_MUX_0_3/AND1_140  (.IN0 (VCC), .IN1 
    (\sub_27/u6/GND ), .OUT (\sub_27/u6/S0_1/CY_MUX_0_3/AND1 ));
    X_OR2 \sub_27/u6/S0_1/CY_MUX_0_3/OR  (.IN0 
    (\sub_27/u6/S0_1/CY_MUX_0_3/AND0 ), .IN1 (\sub_27/u6/S0_1/CY_MUX_0_3/AND1 )
    , .OUT (\sub_27/u6/S0_1/CO_0 ));
    X_CKBUF \U48/clkbuf  (.IN (\U48/clkio_bufsig ), .OUT (n99));
    X_BUF \U48/clkio_buf  (.IN (CLOCK), .OUT (\U48/clkio_bufsig ));
    X_BUF \U1/GR_BUF  (.IN (n100), .OUT (GR));
    X_BUF \U1/GTS_BUF  (.IN (net8), .OUT (GTS));
    X_INV \add_26/u6/S0_1/XOR7_MUX_SEL_1_3_1_INV_181  (.IN (\add_26/n19 ), .OUT 
    (\add_26/u6/S0_1/XOR7_MUX_SEL_1_3_1_INV ));
    X_INV \add_26/u6/S0_1/XOR5_MUX_SEL_1_2_1_INV_182  (.IN (\add_26/n19 ), .OUT 
    (\add_26/u6/S0_1/XOR5_MUX_SEL_1_2_1_INV ));
    X_INV \add_26/u6/S0_1/XOR3_MUX_SEL_1_1_1_INV_183  (.IN (\add_26/n19 ), .OUT 
    (\add_26/u6/S0_1/XOR3_MUX_SEL_1_1_1_INV ));
    X_INV \add_26/u6/S0_1/XOR1_MUX_SEL_1_0_1_INV_184  (.IN (\add_26/n19 ), .OUT 
    (\add_26/u6/S0_1/XOR1_MUX_SEL_1_0_1_INV ));
    X_INV \add_26/u6/S0_1/CY_MUX_1_2/AND0_1_INV_185  (.IN 
    (\add_26/u6/S0_1/MUX_SEL_1_2 ), .OUT 
    (\add_26/u6/S0_1/CY_MUX_1_2/AND0_1_INV ));
    X_INV \add_26/u6/S0_1/CY_MUX_1_1/AND0_1_INV_186  (.IN 
    (\add_26/u6/S0_1/MUX_SEL_1_1 ), .OUT 
    (\add_26/u6/S0_1/CY_MUX_1_1/AND0_1_INV ));
    X_INV \add_26/u6/S0_1/CY_MUX_1_0/AND0_1_INV_187  (.IN 
    (\add_26/u6/S0_1/MUX_SEL_1_0 ), .OUT 
    (\add_26/u6/S0_1/CY_MUX_1_0/AND0_1_INV ));
    X_INV \add_26/u6/S0_1/CY_MUX_0_3/AND0_1_INV_188  (.IN (\add_26/u6/GND ), 
    .OUT (\add_26/u6/S0_1/CY_MUX_0_3/AND0_1_INV ));
    X_INV \sub_27/u6/S0_1/XOR7_MUX_SEL_1_3_1_INV_189  (.IN (\sub_27/n20 ), .OUT 
    (\sub_27/u6/S0_1/XOR7_MUX_SEL_1_3_1_INV ));
    X_INV \sub_27/u6/S0_1/XOR5_MUX_SEL_1_2_1_INV_190  (.IN (\sub_27/n20 ), .OUT 
    (\sub_27/u6/S0_1/XOR5_MUX_SEL_1_2_1_INV ));
    X_INV \sub_27/u6/S0_1/XOR3_MUX_SEL_1_1_1_INV_191  (.IN (\sub_27/n20 ), .OUT 
    (\sub_27/u6/S0_1/XOR3_MUX_SEL_1_1_1_INV ));
    X_INV \sub_27/u6/S0_1/XOR1_MUX_SEL_1_0_1_INV_192  (.IN (\sub_27/n20 ), .OUT 
    (\sub_27/u6/S0_1/XOR1_MUX_SEL_1_0_1_INV ));
    X_INV \sub_27/u6/S0_1/CY_MUX_1_2/AND0_1_INV_193  (.IN 
    (\sub_27/u6/S0_1/MUX_SEL_1_2 ), .OUT 
    (\sub_27/u6/S0_1/CY_MUX_1_2/AND0_1_INV ));
    X_INV \sub_27/u6/S0_1/CY_MUX_1_1/AND0_1_INV_194  (.IN 
    (\sub_27/u6/S0_1/MUX_SEL_1_1 ), .OUT 
    (\sub_27/u6/S0_1/CY_MUX_1_1/AND0_1_INV ));
    X_INV \sub_27/u6/S0_1/CY_MUX_1_0/AND0_1_INV_195  (.IN 
    (\sub_27/u6/S0_1/MUX_SEL_1_0 ), .OUT 
    (\sub_27/u6/S0_1/CY_MUX_1_0/AND0_1_INV ));
    X_INV \sub_27/u6/S0_1/CY_MUX_0_3/AND0_1_INV_196  (.IN (\sub_27/u6/GND ), 
    .OUT (\sub_27/u6/S0_1/CY_MUX_0_3/AND0_1_INV ));
    X_INV \U39/$1I20_GTS_TRI_2_INV_197  (.IN (GTS), .OUT 
    (\U39/$1I20_GTS_TRI_2_INV ));
    X_INV \U40/$1I20_GTS_TRI_2_INV_198  (.IN (GTS), .OUT 
    (\U40/$1I20_GTS_TRI_2_INV ));
    X_INV \U41/$1I20_GTS_TRI_2_INV_199  (.IN (GTS), .OUT 
    (\U41/$1I20_GTS_TRI_2_INV ));
    X_INV \U42/$1I20_GTS_TRI_2_INV_200  (.IN (GTS), .OUT 
    (\U42/$1I20_GTS_TRI_2_INV ));
    X_INV \U43/$1I20_GTS_TRI_2_INV_201  (.IN (GTS), .OUT 
    (\U43/$1I20_GTS_TRI_2_INV ));
    X_INV \U44/$1I20_GTS_TRI_2_INV_202  (.IN (GTS), .OUT 
    (\U44/$1I20_GTS_TRI_2_INV ));
    X_INV \U45/$1I20_GTS_TRI_2_INV_203  (.IN (GTS), .OUT 
    (\U45/$1I20_GTS_TRI_2_INV ));
    X_INV \U46/$1I20_GTS_TRI_2_INV_204  (.IN (GTS), .OUT 
    (\U46/$1I20_GTS_TRI_2_INV ));
    X_ONE VCC_205 (.OUT (VCC));
    X_ZERO GND_206 (.OUT (GND));
  endmodule