time_sim.tv

实用的程序代码

// VERILOG TestFixture Template produced by ngd2ver M1.4.12
// Design file: time_sim.nga
// Date:Tue Jan  6 19:02:58 1998

// ATTENTION: This file was created by NGD2VER and may therefore be overwritten
// by subsequent runs of NGD2VER. Xilinx recommends that you copy this file to
// a new name, or 'paste' this text into another file, to avoid accidental loss
// of data.

`timescale 1 ns/1 ps

module test;
  reg RESET;
  reg CLOCK;
  wire [3:0] DNCNT;
  wire [3:0] UPCNT;

  // To properly simulate your design containing a Startup component,
  // be sure to do the following at the beginning of your simulation:
  // * Toggle your GR port to initialize all registers.
  //
  // To properly simulate your design containing a Startup component,
  // be sure to do the following at the beginning of your simulation:
  // * Deactivate your global tri-state (GTS) control signal.
  //
  use_gr uut ( .RESET (RESET) , .CLOCK (CLOCK) , .DNCNT (DNCNT) , .UPCNT (UPCNT) 
);

  initial begin
    $timeformat(-9,3,"ns",12);
    $shm_open("time_sim.shm");
    $shm_probe("AS");
  end

  initial begin
    $display("           T RCDU");
    $display("           i ELNP");
    $display("           m SOCC");
    $display("           e ECNN");
    $display("             TKTT");
    $display("               [[");
    $display("               33");
    $display("               ::");
    $display("               00");
    $display("               ]]");
    $monitor("%t",$realtime,, RESET, CLOCK, "%h", DNCNT, "%h", UPCNT );
  end

  initial begin
    #100
      RESET = 0 ;
      CLOCK = 0 ;
    #1000 $stop;
    // #1000 $finish;
  end

endmodule