time_sim.v

实用的程序代码

// Xilinx Verilog produced by program ngd2ver, Version M1.4.12
// Date: Tue Jan  6 19:07:56 1998
// Design file: time_sim.nga
// Device: 5202pc84-4
`timescale 1 ns/1 ps
`uselib dir=/home/zeppelin2/tech_apps/m1_4.12/verilog/data libext=.vmd

  module no_gr (RESET, CLOCK, DNCNT, UPCNT);
    input RESET;
    input CLOCK;
    output [3:0] DNCNT;
    output [3:0] UPCNT;

    wire n128, n127, n126, n125, n124, n123, n122, n121, n100, n99, \add_24/n19 
    , \sub_25/n20 , \U39/$1I20_GTS_TRI , \U40/$1I20_GTS_TRI , 
    \U41/$1I20_GTS_TRI , \U42/$1I20_GTS_TRI , \U43/$1I20_GTS_TRI , 
    \U44/$1I20_GTS_TRI , \U45/$1I20_GTS_TRI , \U46/$1I20_GTS_TRI , 
    \UPCNT_reg[3]/$1I13_GR_OR , \UPCNT_reg[2]/$1I13_GR_OR , 
    \UPCNT_reg[1]/$1I13_GR_OR , \UPCNT_reg[0]/$1I13_GR_OR , \DNCNT_reg[3]/D_IN 
    , \DNCNT_reg[3]/Q_OUT , \DNCNT_reg[3]/$1I13_GR_OR , \DNCNT_reg[2]/D_IN , 
    \DNCNT_reg[2]/Q_OUT , \DNCNT_reg[2]/$1I13_GR_OR , \DNCNT_reg[1]/D_IN , 
    \DNCNT_reg[1]/Q_OUT , \DNCNT_reg[1]/$1I13_GR_OR , \DNCNT_reg[0]/D_IN , 
    \DNCNT_reg[0]/Q_OUT , \DNCNT_reg[0]/$1I13_GR_OR , \add_24/u6/S0_1/CO_3 , 
    \add_24/u6/S0_1/MUX_SEL_1_3 , \add_24/u6/S0_1/CO_2 , 
    \add_24/u6/S0_1/MUX_SEL_1_2 , \add_24/u6/S0_1/CO_1 , 
    \add_24/u6/S0_1/MUX_SEL_1_1 , \add_24/u6/S0_1/CO_0 , 
    \add_24/u6/S0_1/MUX_SEL_1_0 , \add_24/u6/GND , 
    \add_24/u6/S0_1/CY_MUX_1_2/AND0 , \add_24/u6/S0_1/CY_MUX_1_2/AND1 , 
    \add_24/u6/S0_1/CY_MUX_1_1/AND0 , \add_24/u6/S0_1/CY_MUX_1_1/AND1 , 
    \add_24/u6/S0_1/CY_MUX_1_0/AND0 , \add_24/u6/S0_1/CY_MUX_1_0/AND1 , 
    \add_24/u6/S0_1/CY_MUX_0_3/AND0 , \add_24/u6/S0_1/CY_MUX_0_3/AND1 , 
    \sub_25/u6/S0_1/CO_3 , \sub_25/u6/S0_1/MUX_SEL_1_3 , \sub_25/u6/S0_1/CO_2 , 
    \sub_25/u6/S0_1/MUX_SEL_1_2 , \sub_25/u6/S0_1/CO_1 , 
    \sub_25/u6/S0_1/MUX_SEL_1_1 , \sub_25/u6/S0_1/CO_0 , 
    \sub_25/u6/S0_1/MUX_SEL_1_0 , \sub_25/u6/GND , 
    \sub_25/u6/S0_1/CY_MUX_1_2/AND0 , \sub_25/u6/S0_1/CY_MUX_1_2/AND1 , 
    \sub_25/u6/S0_1/CY_MUX_1_1/AND0 , \sub_25/u6/S0_1/CY_MUX_1_1/AND1 , 
    \sub_25/u6/S0_1/CY_MUX_1_0/AND0 , \sub_25/u6/S0_1/CY_MUX_1_0/AND1 , 
    \sub_25/u6/S0_1/CY_MUX_0_3/AND0 , \sub_25/u6/S0_1/CY_MUX_0_3/AND1 , 
    \U48/clkio_bufsig , \add_24/u6/S0_1/XOR7_MUX_SEL_1_3_1_INV , 
    \add_24/u6/S0_1/XOR5_MUX_SEL_1_2_1_INV , 
    \add_24/u6/S0_1/XOR3_MUX_SEL_1_1_1_INV , 
    \add_24/u6/S0_1/XOR1_MUX_SEL_1_0_1_INV , 
    \add_24/u6/S0_1/CY_MUX_1_2/AND0_1_INV , 
    \add_24/u6/S0_1/CY_MUX_1_1/AND0_1_INV , 
    \add_24/u6/S0_1/CY_MUX_1_0/AND0_1_INV , 
    \add_24/u6/S0_1/CY_MUX_0_3/AND0_1_INV , 
    \sub_25/u6/S0_1/XOR7_MUX_SEL_1_3_1_INV , 
    \sub_25/u6/S0_1/XOR5_MUX_SEL_1_2_1_INV , 
    \sub_25/u6/S0_1/XOR3_MUX_SEL_1_1_1_INV , 
    \sub_25/u6/S0_1/XOR1_MUX_SEL_1_0_1_INV , 
    \sub_25/u6/S0_1/CY_MUX_1_2/AND0_1_INV , 
    \sub_25/u6/S0_1/CY_MUX_1_1/AND0_1_INV , 
    \sub_25/u6/S0_1/CY_MUX_1_0/AND0_1_INV , 
    \sub_25/u6/S0_1/CY_MUX_0_3/AND0_1_INV , \U39/$1I20_GTS_TRI_2_INV , 
    \U40/$1I20_GTS_TRI_2_INV , \U41/$1I20_GTS_TRI_2_INV , 
    \U42/$1I20_GTS_TRI_2_INV , \U43/$1I20_GTS_TRI_2_INV , 
    \U44/$1I20_GTS_TRI_2_INV , \U45/$1I20_GTS_TRI_2_INV , 
    \U46/$1I20_GTS_TRI_2_INV , GND, VCC;
    wire [3:0] UPCNT37;
    wire [3:0] DNCNT44;
    `ifdef GR_SIGNAL
      wire GR = `GR_SIGNAL ;
    `else
      wire GR ;
    `endif
    `ifdef GTS_SIGNAL
      wire GTS = `GTS_SIGNAL ;
    `else
      wire GTS ;
    `endif
    initial $sdf_annotate("time_sim.sdf");

    X_BUF U47 (.IN (RESET), .OUT (n100));
    X_OPAD \DNCNT<0>_PAD  (.PAD (DNCNT[0]));
    X_OPAD \DNCNT<1>_PAD  (.PAD (DNCNT[1]));
    X_OPAD \DNCNT<2>_PAD  (.PAD (DNCNT[2]));
    X_OPAD \DNCNT<3>_PAD  (.PAD (DNCNT[3]));
    X_OPAD \UPCNT<0>_PAD  (.PAD (UPCNT[0]));
    X_OPAD \UPCNT<1>_PAD  (.PAD (UPCNT[1]));
    X_OPAD \UPCNT<2>_PAD  (.PAD (UPCNT[2]));
    X_OPAD \UPCNT<3>_PAD  (.PAD (UPCNT[3]));
    X_IPAD RESET_PAD (.PAD (RESET));
    X_IPAD CLOCK_PAD (.PAD (CLOCK));
    X_ONE \add_24/n19_ONE  (.OUT (\add_24/n19 ));
    X_ZERO \sub_25/n20_ZERO  (.OUT (\sub_25/n20 ));
    X_BUF \U39/$1I20  (.IN (n128), .OUT (\U39/$1I20_GTS_TRI ));
    X_TRI \U39/$1I20_GTS_TRI_167  (.IN (\U39/$1I20_GTS_TRI ), .OUT (DNCNT[0]), 
    .CTL (\U39/$1I20_GTS_TRI_2_INV ));
    X_BUF \U40/$1I20  (.IN (n127), .OUT (\U40/$1I20_GTS_TRI ));
    X_TRI \U40/$1I20_GTS_TRI_168  (.IN (\U40/$1I20_GTS_TRI ), .OUT (DNCNT[1]), 
    .CTL (\U40/$1I20_GTS_TRI_2_INV ));
    X_BUF \U41/$1I20  (.IN (n126), .OUT (\U41/$1I20_GTS_TRI ));
    X_TRI \U41/$1I20_GTS_TRI_169  (.IN (\U41/$1I20_GTS_TRI ), .OUT (DNCNT[2]), 
    .CTL (\U41/$1I20_GTS_TRI_2_INV ));
    X_BUF \U42/$1I20  (.IN (n125), .OUT (\U42/$1I20_GTS_TRI ));
    X_TRI \U42/$1I20_GTS_TRI_170  (.IN (\U42/$1I20_GTS_TRI ), .OUT (DNCNT[3]), 
    .CTL (\U42/$1I20_GTS_TRI_2_INV ));
    X_BUF \U43/$1I20  (.IN (n124), .OUT (\U43/$1I20_GTS_TRI ));
    X_TRI \U43/$1I20_GTS_TRI_171  (.IN (\U43/$1I20_GTS_TRI ), .OUT (UPCNT[0]), 
    .CTL (\U43/$1I20_GTS_TRI_2_INV ));
    X_BUF \U44/$1I20  (.IN (n123), .OUT (\U44/$1I20_GTS_TRI ));
    X_TRI \U44/$1I20_GTS_TRI_172  (.IN (\U44/$1I20_GTS_TRI ), .OUT (UPCNT[1]), 
    .CTL (\U44/$1I20_GTS_TRI_2_INV ));
    X_BUF \U45/$1I20  (.IN (n122), .OUT (\U45/$1I20_GTS_TRI ));
    X_TRI \U45/$1I20_GTS_TRI_173  (.IN (\U45/$1I20_GTS_TRI ), .OUT (UPCNT[2]), 
    .CTL (\U45/$1I20_GTS_TRI_2_INV ));
    X_BUF \U46/$1I20  (.IN (n121), .OUT (\U46/$1I20_GTS_TRI ));
    X_TRI \U46/$1I20_GTS_TRI_174  (.IN (\U46/$1I20_GTS_TRI ), .OUT (UPCNT[3]), 
    .CTL (\U46/$1I20_GTS_TRI_2_INV ));
    X_FF \UPCNT_reg<3>/$1I13  (.IN (UPCNT37[3]), .CLK (n99), .CE (VCC), .SET 
    (GND), .RST (\UPCNT_reg[3]/$1I13_GR_OR ), .OUT (n121));
    X_OR2 \UPCNT_reg<3>/$1I13_GR_OR_159  (.IN0 (n100), .IN1 (GR), .OUT 
    (\UPCNT_reg[3]/$1I13_GR_OR ));
    X_FF \UPCNT_reg<2>/$1I13  (.IN (UPCNT37[2]), .CLK (n99), .CE (VCC), .SET 
    (GND), .RST (\UPCNT_reg[2]/$1I13_GR_OR ), .OUT (n122));
    X_OR2 \UPCNT_reg<2>/$1I13_GR_OR_160  (.IN0 (n100), .IN1 (GR), .OUT 
    (\UPCNT_reg[2]/$1I13_GR_OR ));
    X_FF \UPCNT_reg<1>/$1I13  (.IN (UPCNT37[1]), .CLK (n99), .CE (VCC), .SET 
    (GND), .RST (\UPCNT_reg[1]/$1I13_GR_OR ), .OUT (n123));
    X_OR2 \UPCNT_reg<1>/$1I13_GR_OR_161  (.IN0 (n100), .IN1 (GR), .OUT 
    (\UPCNT_reg[1]/$1I13_GR_OR ));
    X_FF \UPCNT_reg<0>/$1I13  (.IN (UPCNT37[0]), .CLK (n99), .CE (VCC), .SET 
    (GND), .RST (\UPCNT_reg[0]/$1I13_GR_OR ), .OUT (n124));
    X_OR2 \UPCNT_reg<0>/$1I13_GR_OR_162  (.IN0 (n100), .IN1 (GR), .OUT 
    (\UPCNT_reg[0]/$1I13_GR_OR ));
    X_INV \DNCNT_reg<3>/SYM1  (.IN (DNCNT44[3]), .OUT (\DNCNT_reg[3]/D_IN ));
    X_INV \DNCNT_reg<3>/SYM2  (.IN (\DNCNT_reg[3]/Q_OUT ), .OUT (n125));
    X_FF \DNCNT_reg<3>/$1I13  (.IN (\DNCNT_reg[3]/D_IN ), .CLK (n99), .CE (VCC)
    , .SET (GND), .RST (\DNCNT_reg[3]/$1I13_GR_OR ), .OUT (\DNCNT_reg[3]/Q_OUT )
    );
    X_OR2 \DNCNT_reg<3>/$1I13_GR_OR_163  (.IN0 (n100), .IN1 (GR), .OUT 
    (\DNCNT_reg[3]/$1I13_GR_OR ));
    X_INV \DNCNT_reg<2>/SYM1  (.IN (DNCNT44[2]), .OUT (\DNCNT_reg[2]/D_IN ));
    X_INV \DNCNT_reg<2>/SYM2  (.IN (\DNCNT_reg[2]/Q_OUT ), .OUT (n126));
    X_FF \DNCNT_reg<2>/$1I13  (.IN (\DNCNT_reg[2]/D_IN ), .CLK (n99), .CE (VCC)
    , .SET (GND), .RST (\DNCNT_reg[2]/$1I13_GR_OR ), .OUT (\DNCNT_reg[2]/Q_OUT )
    );
    X_OR2 \DNCNT_reg<2>/$1I13_GR_OR_164  (.IN0 (n100), .IN1 (GR), .OUT 
    (\DNCNT_reg[2]/$1I13_GR_OR ));
    X_INV \DNCNT_reg<1>/SYM1  (.IN (DNCNT44[1]), .OUT (\DNCNT_reg[1]/D_IN ));
    X_INV \DNCNT_reg<1>/SYM2  (.IN (\DNCNT_reg[1]/Q_OUT ), .OUT (n127));
    X_FF \DNCNT_reg<1>/$1I13  (.IN (\DNCNT_reg[1]/D_IN ), .CLK (n99), .CE (VCC)
    , .SET (GND), .RST (\DNCNT_reg[1]/$1I13_GR_OR ), .OUT (\DNCNT_reg[1]/Q_OUT )
    );
    X_OR2 \DNCNT_reg<1>/$1I13_GR_OR_165  (.IN0 (n100), .IN1 (GR), .OUT 
    (\DNCNT_reg[1]/$1I13_GR_OR ));
    X_INV \DNCNT_reg<0>/SYM1  (.IN (DNCNT44[0]), .OUT (\DNCNT_reg[0]/D_IN ));
    X_INV \DNCNT_reg<0>/SYM2  (.IN (\DNCNT_reg[0]/Q_OUT ), .OUT (n128));
    X_FF \DNCNT_reg<0>/$1I13  (.IN (\DNCNT_reg[0]/D_IN ), .CLK (n99), .CE (VCC)
    , .SET (GND), .RST (\DNCNT_reg[0]/$1I13_GR_OR ), .OUT (\DNCNT_reg[0]/Q_OUT )
    );
    X_OR2 \DNCNT_reg<0>/$1I13_GR_OR_166  (.IN0 (n100), .IN1 (GR), .OUT 
    (\DNCNT_reg[0]/$1I13_GR_OR ));
    X_XOR2 \add_24/u6/S0_1/XOR8_SUM_1_3  (.IN0 (\add_24/u6/S0_1/CO_3 ), .IN1 
    (\add_24/u6/S0_1/MUX_SEL_1_3 ), .OUT (UPCNT37[3]));
    X_XOR2 \add_24/u6/S0_1/XOR7_MUX_SEL_1_3  (.IN0 (n121), .IN1 
    (\add_24/u6/S0_1/XOR7_MUX_SEL_1_3_1_INV ), .OUT 
    (\add_24/u6/S0_1/MUX_SEL_1_3 ));
    X_XOR2 \add_24/u6/S0_1/XOR6_SUM_1_2  (.IN0 (\add_24/u6/S0_1/CO_2 ), .IN1 
    (\add_24/u6/S0_1/MUX_SEL_1_2 ), .OUT (UPCNT37[2]));
    X_XOR2 \add_24/u6/S0_1/XOR5_MUX_SEL_1_2  (.IN0 (n122), .IN1 
    (\add_24/u6/S0_1/XOR5_MUX_SEL_1_2_1_INV ), .OUT 
    (\add_24/u6/S0_1/MUX_SEL_1_2 ));
    X_XOR2 \add_24/u6/S0_1/XOR4_SUM_1_1  (.IN0 (\add_24/u6/S0_1/CO_1 ), .IN1