active_low_gr.twr

实用的程序代码

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Xilinx TRACE, Version M1.4.12
Copyright (c) 1995-1997 Xilinx, Inc.  All rights reserved.

Design file:              active_low_gr.ncd
Physical constraint file: active_low_gr.pcf
Device,speed:             xc5202,-4 (1.35__5200.5_5202.13)
Report level:             summary report
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WARNING:bastw:172 - No timing constraints found, doing advanced analysis with
   offsets.

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Timing constraint: Default period analysis for net n99
 28 items analyzed, 0 timing errors detected.
 Minimum period is  18.219ns.
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================================================================================
Timing constraint: Default OFFSET IN BEFORE analysis for clock "n99"
 8 items analyzed, 0 timing errors detected.
 Minimum allowable offset is   3.741ns.
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================================================================================
Timing constraint: Default OFFSET OUT AFTER analysis for clock "n99"
 8 items analyzed, 0 timing errors detected.
 Maximum allowable offset is  17.533ns.
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================================================================================
Timing constraint: Default path analysis
 17 items analyzed, 0 timing errors detected.
 Maximum delay is  13.470ns.
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All constraints were met.


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 53 paths, 0 nets, and 65 connections (91.5% coverage)

Design statistics:
   Minimum period:  18.219ns (Maximum frequency:  54.888MHz)
   Maximum combinational path delay:  13.470ns
   Minimum input arrival time before clock:   3.741ns
   Maximum output required time before clock:  17.533ns


Analysis completed Tue Jan  6 19:05:22 1998
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