time_sim.vhd

实用的程序代码

-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 16:15:18 1998
-- Design file: time_sim.nga
-- Device: 4005epc84-2
----- CELL ROC -----
-- Model for  Reset-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity ROC is
    generic ( InstancePath: STRING := "*";
              WIDTH : Time := 0 ns) ;
    port( O : out std_ulogic := '1' ) ;
    attribute VITAL_LEVEL0 of ROC : entity is TRUE ;
end ROC ;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      if (WIDTH <= 0 ns) then
         assert FALSE report
         "*** Error: a positive value of WIDTH must be specified ***"
         severity failure;
      else
         wait for WIDTH;
         O <= '0' ;
      end if;
      wait;
    end process ONE_SHOT ;
end ROC_V ;

configuration CFG_ROC_V of ROC is
    for ROC_V
    end for ;
end CFG_ROC_V ;
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity NESTED_IF is
  port (
    RESET : in STD_LOGIC := 'X' ;
    CLK : in STD_LOGIC := 'X' ;
    ADDR_A : in  STD_LOGIC_VECTOR ( 1 downto 0 );
    ADDR_B : in  STD_LOGIC_VECTOR ( 1 downto 0 );
    ADDR_C : in  STD_LOGIC_VECTOR ( 1 downto 0 );
    ADDR_D : in  STD_LOGIC_VECTOR ( 1 downto 0 );
    DEC_Q : out  STD_LOGIC_VECTOR ( 5 downto 0 )
  ) ;
end NESTED_IF ;

architecture STRUCTURE of NESTED_IF is
  component ROC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal N388 , N390 , N392 , N393 , N394 , N395 , N396 , N397 , N463 , N444 , 
  N464 , N443 , N465 , N466 , N469 , N468 , N467 , N470 , N473 , N472 , N471 , 
  N440 , N475 , N474 , N476 , DEC_Q_REG_5_1I11_QINT , 
  DEC_Q_REG_5_1I11_OBUF_GTS_TRI , DEC_Q_REG_4_1I11_QINT , 
  DEC_Q_REG_4_1I11_OBUF_GTS_TRI , DEC_Q_REG_3_1I11_QINT , 
  DEC_Q_REG_3_1I11_OBUF_GTS_TRI , DEC_Q_REG_2_1I11_QINT , 
  DEC_Q_REG_2_1I11_OBUF_GTS_TRI , DEC_Q_REG_1_1I11_QINT , 
  DEC_Q_REG_1_1I11_OBUF_GTS_TRI , DEC_Q_REG_0_1I11_QINT , 
  DEC_Q_REG_0_1I11_OBUF_GTS_TRI , U123_CLKIO_BUFSIG , U129_2_0 , U140_2_0 , 
  U146_2_0 , U146_2_1 , U125_2_INV , U128_2_INV , U132_2_INV , U133_2_INV , 
  U135_2_INV , U137_2_INV , U138_2_INV , U139_2_INV , U141_2_INV , U144_2_INV , 
  U129_DEC_Q60_1_2_INV , U140_DEC_Q60_0_2_INV , 
  DEC_Q_REG_5_1I11_OBUF_GTS_TRI_2_INV , DEC_Q_REG_4_1I11_OBUF_GTS_TRI_2_INV , 
  DEC_Q_REG_3_1I11_OBUF_GTS_TRI_2_INV , DEC_Q_REG_2_1I11_OBUF_GTS_TRI_2_INV , 
  DEC_Q_REG_1_1I11_OBUF_GTS_TRI_2_INV , DEC_Q_REG_0_1I11_OBUF_GTS_TRI_2_INV , 
  GND , VCC , GSR , GTS : STD_LOGIC ;
  signal ADD_36_PLUS_CARRY : STD_LOGIC_VECTOR ( 1 downto 1 );
  signal R23_CARRY : STD_LOGIC_VECTOR ( 1 downto 1 );
  signal DEC_Q60 : STD_LOGIC_VECTOR ( 5 downto 0 );
  begin
    U114 : X_BUF 
      port map ( I => ADDR_A(1) , O => N388 ) ;
    U115 : X_BUF 
      port map ( I => ADDR_A(0) , O => ADD_36_PLUS_CARRY(1) ) ;
    U116 : X_BUF 
      port map ( I => ADDR_B(1) , O => N390 ) ;
    U117 : X_BUF 
      port map ( I => ADDR_B(0) , O => R23_CARRY(1) ) ;
    U118 : X_BUF 
      port map ( I => ADDR_C(1) , O => N392 ) ;
    U119 : X_BUF 
      port map ( I => ADDR_C(0) , O => N393 ) ;
    U120 : X_BUF 
      port map ( I => ADDR_D(1) , O => N394 ) ;
    U121 : X_BUF 
      port map ( I => ADDR_D(0) , O => N395 ) ;
    U122 : X_BUF 
      port map ( I => RESET , O => N396 ) ;
    U124 : X_INV 
      port map ( I => R23_CARRY(1) , O => N463 ) ;
    U125 : X_OR2 
      port map ( I0 => N390 , I1 => N463 , O => U125_2_INV ) ;
    U126 : X_OR2 
      port map ( I0 => N443 , I1 => R23_CARRY(1) , O => N464 ) ;
    U127 : X_AND2 
      port map ( I0 => N464 , I1 => N390 , O => N465 ) ;
    U128 : X_OR2 
      port map ( I0 => N390 , I1 => R23_CARRY(1) , O => U128_2_INV ) ;
    U130 : X_INV 
      port map ( I => N468 , O => N469 ) ;
    U131 : X_INV 
      port map ( I => ADD_36_PLUS_CARRY(1) , O => N467 ) ;
    U132 : X_AND2 
      port map ( I0 => N467 , I1 => N388 , O => U132_2_INV ) ;
    U133 : X_OR2 
      port map ( I0 => N469 , I1 => N396 , O => U133_2_INV ) ;
    U134 : X_INV 
      port map ( I => N388 , O => N470 ) ;
    U135 : X_OR2 
      port map ( I0 => N396 , I1 => N470 , O => U135_2_INV ) ;
    U136 : X_INV 
      port map ( I => N472 , O => N473 ) ;
    U137 : X_AND2 
      port map ( I0 => N440 , I1 => N395 , O => U137_2_INV ) ;
    U138 : X_XOR2 
      port map ( I0 => N394 , I1 => N471 , O => U138_2_INV ) ;
    U139 : X_OR2 
      port map ( I0 => N473 , I1 => N396 , O => U139_2_INV ) ;
    U141 : X_OR2 
      port map ( I0 => ADD_36_PLUS_CARRY(1) , I1 => N388 , O => U141_2_INV ) ;
    U142 : X_INV 
      port map ( I => N474 , O => N475 ) ;
    U143 : X_XOR2 
      port map ( I0 => N440 , I1 => N395 , O => N474 ) ;
    U144 : X_OR2 
      port map ( I0 => N475 , I1 => N396 , O => U144_2_INV ) ;
    U145 : X_INV 
      port map ( I => N393 , O => N476 ) ;
    DEC_Q_REG_5_1I11_FF : X_FF 
      port map ( I => DEC_Q60(5) , CLK => N397 , CE => VCC , SET => GND , 
      RST => GSR , O => DEC_Q_REG_5_1I11_QINT ) ;
    DEC_Q_REG_5_1I11_OBUF : X_BUF 
      port map ( I => DEC_Q_REG_5_1I11_QINT , 
      O => DEC_Q_REG_5_1I11_OBUF_GTS_TRI ) ;
    DEC_Q_REG_5_1I11_OBUF_GTS_TRI_0 : X_TRI 
      port map ( I => DEC_Q_REG_5_1I11_OBUF_GTS_TRI , O => DEC_Q(5) , 
      CTL => DEC_Q_REG_5_1I11_OBUF_GTS_TRI_2_INV ) ;
    DEC_Q_REG_4_1I11_FF : X_FF 
      port map ( I => DEC_Q60(4) , CLK => N397 , CE => VCC , SET => GND , 
      RST => GSR , O => DEC_Q_REG_4_1I11_QINT ) ;
    DEC_Q_REG_4_1I11_OBUF : X_BUF 
      port map ( I => DEC_Q_REG_4_1I11_QINT , 
      O => DEC_Q_REG_4_1I11_OBUF_GTS_TRI ) ;
    DEC_Q_REG_4_1I11_OBUF_GTS_TRI_1 : X_TRI 
      port map ( I => DEC_Q_REG_4_1I11_OBUF_GTS_TRI , O => DEC_Q(4) , 
      CTL => DEC_Q_REG_4_1I11_OBUF_GTS_TRI_2_INV ) ;
    DEC_Q_REG_3_1I11_FF : X_FF 
      port map ( I => DEC_Q60(3) , CLK => N397 , CE => VCC , SET => GND , 
      RST => GSR , O => DEC_Q_REG_3_1I11_QINT ) ;
    DEC_Q_REG_3_1I11_OBUF : X_BUF 
      port map ( I => DEC_Q_REG_3_1I11_QINT , 
      O => DEC_Q_REG_3_1I11_OBUF_GTS_TRI ) ;
    DEC_Q_REG_3_1I11_OBUF_GTS_TRI_2 : X_TRI 
      port map ( I => DEC_Q_REG_3_1I11_OBUF_GTS_TRI , O => DEC_Q(3) , 
      CTL => DEC_Q_REG_3_1I11_OBUF_GTS_TRI_2_INV ) ;
    DEC_Q_REG_2_1I11_FF : X_FF 
      port map ( I => DEC_Q60(2) , CLK => N397 , CE => VCC , SET => GND , 
      RST => GSR , O => DEC_Q_REG_2_1I11_QINT ) ;
    DEC_Q_REG_2_1I11_OBUF : X_BUF 
      port map ( I => DEC_Q_REG_2_1I11_QINT , 
      O => DEC_Q_REG_2_1I11_OBUF_GTS_TRI ) ;
    DEC_Q_REG_2_1I11_OBUF_GTS_TRI_3 : X_TRI 
      port map ( I => DEC_Q_REG_2_1I11_OBUF_GTS_TRI , O => DEC_Q(2) , 
      CTL => DEC_Q_REG_2_1I11_OBUF_GTS_TRI_2_INV ) ;
    DEC_Q_REG_1_1I11_FF : X_FF 
      port map ( I => DEC_Q60(1) , CLK => N397 , CE => VCC , SET => GND , 
      RST => GSR , O => DEC_Q_REG_1_1I11_QINT ) ;
    DEC_Q_REG_1_1I11_OBUF : X_BUF 
      port map ( I => DEC_Q_REG_1_1I11_QINT , 
      O => DEC_Q_REG_1_1I11_OBUF_GTS_TRI ) ;
    DEC_Q_REG_1_1I11_OBUF_GTS_TRI_4 : X_TRI 
      port map ( I => DEC_Q_REG_1_1I11_OBUF_GTS_TRI , O => DEC_Q(1) , 
      CTL => DEC_Q_REG_1_1I11_OBUF_GTS_TRI_2_INV ) ;
    DEC_Q_REG_0_1I11_FF : X_FF 
      port map ( I => DEC_Q60(0) , CLK => N397 , CE => VCC , SET => GND , 
      RST => GSR , O => DEC_Q_REG_0_1I11_QINT ) ;
    DEC_Q_REG_0_1I11_OBUF : X_BUF 
      port map ( I => DEC_Q_REG_0_1I11_QINT , 
      O => DEC_Q_REG_0_1I11_OBUF_GTS_TRI ) ;
    DEC_Q_REG_0_1I11_OBUF_GTS_TRI_5 : X_TRI 
      port map ( I => DEC_Q_REG_0_1I11_OBUF_GTS_TRI , O => DEC_Q(0) , 
      CTL => DEC_Q_REG_0_1I11_OBUF_GTS_TRI_2_INV ) ;
    U123_CLKBUF : X_CKBUF 
      port map ( I => U123_CLKIO_BUFSIG , O => N397 ) ;
    U123_CLKIO_BUF : X_BUF 
      port map ( I => CLK , O => U123_CLKIO_BUFSIG ) ;
    U129_DEC_Q60_1_2_0 : X_OR2 
      port map ( I0 => N396 , I1 => N466 , O => U129_2_0 ) ;
    U129_DEC_Q60_1_Q : X_OR2 
      port map ( I0 => U129_2_0 , I1 => N465 , O => U129_DEC_Q60_1_2_INV ) ;
    U140_DEC_Q60_0_2_0 : X_OR2 
      port map ( I0 => N443 , I1 => R23_CARRY(1) , O => U140_2_0 ) ;
    U140_DEC_Q60_0_Q : X_OR2 
      port map ( I0 => U140_2_0 , I1 => N396 , O => U140_DEC_Q60_0_2_INV ) ;
    U146_N440_2_0 : X_AND2 
      port map ( I0 => N392 , I1 => N444 , O => U146_2_0 ) ;
    U146_N440_2_1 : X_AND2 
      port map ( I0 => N443 , I1 => N476 , O => U146_2_1 ) ;
    U146_N440 : X_AND2 
      port map ( I0 => U146_2_0 , I1 => U146_2_1 , O => N440 ) ;
    U125_2_INV_6 : X_INV 
      port map ( I => U125_2_INV , O => N444 ) ;
    U128_2_INV_7 : X_INV 
      port map ( I => U128_2_INV , O => N466 ) ;
    U132_2_INV_8 : X_INV 
      port map ( I => U132_2_INV , O => N468 ) ;
    U133_2_INV_9 : X_INV 
      port map ( I => U133_2_INV , O => DEC_Q60(2) ) ;
    U135_2_INV_10 : X_INV 
      port map ( I => U135_2_INV , O => DEC_Q60(3) ) ;
    U137_2_INV_11 : X_INV 
      port map ( I => U137_2_INV , O => N471 ) ;
    U138_2_INV_12 : X_INV 
      port map ( I => U138_2_INV , O => N472 ) ;
    U139_2_INV_13 : X_INV 
      port map ( I => U139_2_INV , O => DEC_Q60(5) ) ;
    U141_2_INV_14 : X_INV 
      port map ( I => U141_2_INV , O => N443 ) ;
    U144_2_INV_15 : X_INV 
      port map ( I => U144_2_INV , O => DEC_Q60(4) ) ;
    U129_DEC_Q60_1_2_INV_16 : X_INV 
      port map ( I => U129_DEC_Q60_1_2_INV , O => DEC_Q60(1) ) ;
    U140_DEC_Q60_0_2_INV_17 : X_INV 
      port map ( I => U140_DEC_Q60_0_2_INV , O => DEC_Q60(0) ) ;
    DEC_Q_REG_5_1I11_OBUF_GTS_TRI_2_INV_18 : X_INV 
      port map ( I => GTS , O => DEC_Q_REG_5_1I11_OBUF_GTS_TRI_2_INV ) ;
    DEC_Q_REG_4_1I11_OBUF_GTS_TRI_2_INV_19 : X_INV 
      port map ( I => GTS , O => DEC_Q_REG_4_1I11_OBUF_GTS_TRI_2_INV ) ;
    DEC_Q_REG_3_1I11_OBUF_GTS_TRI_2_INV_20 : X_INV 
      port map ( I => GTS , O => DEC_Q_REG_3_1I11_OBUF_GTS_TRI_2_INV ) ;
    DEC_Q_REG_2_1I11_OBUF_GTS_TRI_2_INV_21 : X_INV 
      port map ( I => GTS , O => DEC_Q_REG_2_1I11_OBUF_GTS_TRI_2_INV ) ;
    DEC_Q_REG_1_1I11_OBUF_GTS_TRI_2_INV_22 : X_INV 
      port map ( I => GTS , O => DEC_Q_REG_1_1I11_OBUF_GTS_TRI_2_INV ) ;
    DEC_Q_REG_0_1I11_OBUF_GTS_TRI_2_INV_23 : X_INV 
      port map ( I => GTS , O => DEC_Q_REG_0_1I11_OBUF_GTS_TRI_2_INV ) ;
    VCC_24 : X_ONE 
      port map ( O => VCC ) ;
    GND_25 : X_ZERO 
      port map ( O => GND ) ;
    ROC_NGD2VHDL : ROC 
      port map ( O => GSR ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;