time_sim.v

实用的程序代码

// Xilinx Verilog produced by program ngd2ver, Version M1.4.12
// Date: Tue Jan  6 18:19:10 1998
// Design file: time_sim.nga
// Device: 4005epc84-2
`timescale 1 ns/1 ps
`uselib dir=/home/zeppelin2/tech_apps/m1_4.12/verilog/data libext=.vmd

  module nested_if (RESET, CLK, ADDR_A, ADDR_B, ADDR_C, ADDR_D, DEC_Q);
    input RESET;
    input CLK;
    input [1:0] ADDR_A;
    input [1:0] ADDR_B;
    input [1:0] ADDR_C;
    input [1:0] ADDR_D;
    output [5:0] DEC_Q;

    wire n256, n257, n258, n260, n261, n262, n264, n265, n333, n336, n309, n334
    , n339, n310, n338, n335, n337, n311, n340, n341, n342, n343, n346, n345, 
    n344, n349, n348, n347, \DEC_Q_reg[5]/$1I11/QINT , 
    \DEC_Q_reg[5]/$1I11/OBUF_GTS_TRI , \DEC_Q_reg[4]/$1I11/QINT , 
    \DEC_Q_reg[4]/$1I11/OBUF_GTS_TRI , \DEC_Q_reg[3]/$1I11/QINT , 
    \DEC_Q_reg[3]/$1I11/OBUF_GTS_TRI , \DEC_Q_reg[2]/$1I11/QINT , 
    \DEC_Q_reg[2]/$1I11/OBUF_GTS_TRI , \DEC_Q_reg[1]/$1I11/QINT , 
    \DEC_Q_reg[1]/$1I11/OBUF_GTS_TRI , \DEC_Q_reg[0]/$1I11/QINT , 
    \DEC_Q_reg[0]/$1I11/OBUF_GTS_TRI , \U131/clkio_bufsig , \U136/2_0 , 
    \U147/2_0 , \U147/2_1 , \U149/2_0 , U140_2_INV, U142_2_INV, U152_2_INV, 
    U157_2_INV, \U136/n339_2_INV , \U147/n310_2_INV , \U149/n309_2_INV , 
    \DEC_Q_reg[5]/$1I11/OBUF_GTS_TRI_2_INV , 
    \DEC_Q_reg[4]/$1I11/OBUF_GTS_TRI_2_INV , 
    \DEC_Q_reg[3]/$1I11/OBUF_GTS_TRI_2_INV , 
    \DEC_Q_reg[2]/$1I11/OBUF_GTS_TRI_2_INV , 
    \DEC_Q_reg[1]/$1I11/OBUF_GTS_TRI_2_INV , 
    \DEC_Q_reg[0]/$1I11/OBUF_GTS_TRI_2_INV , GND, VCC;
    wire [1:1] \r24/carry ;
    wire [1:1] \add_35/carry ;
    wire [5:0] DEC_Q109;
    `ifdef GSR_SIGNAL
      wire GSR = `GSR_SIGNAL ;
    `else
      wire GSR ;
    `endif
    `ifdef GTS_SIGNAL
      wire GTS = `GTS_SIGNAL ;
    `else
      wire GTS ;
    `endif
    initial $sdf_annotate("time_sim.sdf");

    X_BUF U122 (.IN (ADDR_A[1]), .OUT (n256));
    X_BUF U123 (.IN (ADDR_A[0]), .OUT (n257));
    X_BUF U124 (.IN (ADDR_B[1]), .OUT (n258));
    X_BUF U125 (.IN (ADDR_B[0]), .OUT (\r24/carry [1]));
    X_BUF U126 (.IN (ADDR_C[1]), .OUT (n260));
    X_BUF U127 (.IN (ADDR_C[0]), .OUT (n261));
    X_BUF U128 (.IN (ADDR_D[1]), .OUT (n262));
    X_BUF U129 (.IN (ADDR_D[0]), .OUT (\add_35/carry [1]));
    X_BUF U130 (.IN (RESET), .OUT (n264));
    X_XOR2 U132 (.IN0 (\r24/carry [1]), .IN1 (n258), .OUT (n333));
    X_AND2 U133 (.IN0 (n333), .IN1 (n264), .OUT (DEC_Q109[1]));
    X_INV U134 (.IN (n309), .OUT (n336));
    X_INV U135 (.IN (\add_35/carry [1]), .OUT (n334));
    X_OR2 U137 (.IN0 (n335), .IN1 (n334), .OUT (n338));
    X_AND2 U138 (.IN0 (n337), .IN1 (n311), .OUT (n335));
    X_OR2 U139 (.IN0 (n310), .IN1 (n336), .OUT (n337));
    X_AND2 U140 (.IN0 (n338), .IN1 (n339), .OUT (U140_2_INV));
    X_INV U141 (.IN (n264), .OUT (n340));
    X_OR2 U142 (.IN0 (\r24/carry [1]), .IN1 (n340), .OUT (U142_2_INV));
    X_AND2 U143 (.IN0 (n257), .IN1 (n264), .OUT (DEC_Q109[2]));
    X_AND2 U144 (.IN0 (n256), .IN1 (n264), .OUT (DEC_Q109[3]));
    X_INV U145 (.IN (n260), .OUT (n341));
    X_INV U146 (.IN (\r24/carry [1]), .OUT (n342));
    X_INV U148 (.IN (n264), .OUT (n343));
    X_INV U150 (.IN (n345), .OUT (n346));
    X_INV U151 (.IN (n311), .OUT (n344));
    X_AND2 U152 (.IN0 (n344), .IN1 (n262), .OUT (U152_2_INV));
    X_OR2 U153 (.IN0 (n349), .IN1 (n346), .OUT (DEC_Q109[5]));
    X_XOR2 U154 (.IN0 (n347), .IN1 (n262), .OUT (n348));
    X_AND2 U155 (.IN0 (n310), .IN1 (\add_35/carry [1]), .OUT (n347));
    X_AND2 U156 (.IN0 (n348), .IN1 (n309), .OUT (n349));
    X_OR2 U157 (.IN0 (DEC_Q109[2]), .IN1 (DEC_Q109[3]), .OUT (U157_2_INV));
    X_IPAD \ADDR_A<1>_PAD  (.PAD (ADDR_A[1]));
    X_IPAD \ADDR_A<0>_PAD  (.PAD (ADDR_A[0]));
    X_IPAD \ADDR_B<1>_PAD  (.PAD (ADDR_B[1]));
    X_IPAD \ADDR_B<0>_PAD  (.PAD (ADDR_B[0]));
    X_IPAD \ADDR_C<1>_PAD  (.PAD (ADDR_C[1]));
    X_IPAD \ADDR_C<0>_PAD  (.PAD (ADDR_C[0]));
    X_IPAD \ADDR_D<1>_PAD  (.PAD (ADDR_D[1]));
    X_IPAD \ADDR_D<0>_PAD  (.PAD (ADDR_D[0]));
    X_IPAD RESET_PAD (.PAD (RESET));
    X_IPAD CLK_PAD (.PAD (CLK));
    X_OPAD \DEC_Q<5>_PAD  (.PAD (DEC_Q[5]));
    X_OPAD \DEC_Q<4>_PAD  (.PAD (DEC_Q[4]));
    X_OPAD \DEC_Q<3>_PAD  (.PAD (DEC_Q[3]));
    X_OPAD \DEC_Q<2>_PAD  (.PAD (DEC_Q[2]));
    X_OPAD \DEC_Q<1>_PAD  (.PAD (DEC_Q[1]));
    X_OPAD \DEC_Q<0>_PAD  (.PAD (DEC_Q[0]));
    X_FF \DEC_Q_reg<5>/$1I11/FF  (.IN (DEC_Q109[5]), .CLK (n265), .CE (VCC), 
    .SET (GND), .RST (GSR), .OUT (\DEC_Q_reg[5]/$1I11/QINT ));
    X_BUF \DEC_Q_reg<5>/$1I11/OBUF  (.IN (\DEC_Q_reg[5]/$1I11/QINT ), .OUT 
    (\DEC_Q_reg[5]/$1I11/OBUF_GTS_TRI ));
    X_TRI \DEC_Q_reg<5>/$1I11/OBUF_GTS_TRI_102  (.IN 
    (\DEC_Q_reg[5]/$1I11/OBUF_GTS_TRI ), .OUT (DEC_Q[5]), .CTL 
    (\DEC_Q_reg[5]/$1I11/OBUF_GTS_TRI_2_INV ));
    X_FF \DEC_Q_reg<4>/$1I11/FF  (.IN (DEC_Q109[4]), .CLK (n265), .CE (VCC), 
    .SET (GND), .RST (GSR), .OUT (\DEC_Q_reg[4]/$1I11/QINT ));
    X_BUF \DEC_Q_reg<4>/$1I11/OBUF  (.IN (\DEC_Q_reg[4]/$1I11/QINT ), .OUT 
    (\DEC_Q_reg[4]/$1I11/OBUF_GTS_TRI ));
    X_TRI \DEC_Q_reg<4>/$1I11/OBUF_GTS_TRI_103  (.IN 
    (\DEC_Q_reg[4]/$1I11/OBUF_GTS_TRI ), .OUT (DEC_Q[4]), .CTL 
    (\DEC_Q_reg[4]/$1I11/OBUF_GTS_TRI_2_INV ));
    X_FF \DEC_Q_reg<3>/$1I11/FF  (.IN (DEC_Q109[3]), .CLK (n265), .CE (VCC), 
    .SET (GND), .RST (GSR), .OUT (\DEC_Q_reg[3]/$1I11/QINT ));
    X_BUF \DEC_Q_reg<3>/$1I11/OBUF  (.IN (\DEC_Q_reg[3]/$1I11/QINT ), .OUT 
    (\DEC_Q_reg[3]/$1I11/OBUF_GTS_TRI ));
    X_TRI \DEC_Q_reg<3>/$1I11/OBUF_GTS_TRI_104  (.IN 
    (\DEC_Q_reg[3]/$1I11/OBUF_GTS_TRI ), .OUT (DEC_Q[3]), .CTL 
    (\DEC_Q_reg[3]/$1I11/OBUF_GTS_TRI_2_INV ));
    X_FF \DEC_Q_reg<2>/$1I11/FF  (.IN (DEC_Q109[2]), .CLK (n265), .CE (VCC), 
    .SET (GND), .RST (GSR), .OUT (\DEC_Q_reg[2]/$1I11/QINT ));
    X_BUF \DEC_Q_reg<2>/$1I11/OBUF  (.IN (\DEC_Q_reg[2]/$1I11/QINT ), .OUT 
    (\DEC_Q_reg[2]/$1I11/OBUF_GTS_TRI ));
    X_TRI \DEC_Q_reg<2>/$1I11/OBUF_GTS_TRI_105  (.IN 
    (\DEC_Q_reg[2]/$1I11/OBUF_GTS_TRI ), .OUT (DEC_Q[2]), .CTL 
    (\DEC_Q_reg[2]/$1I11/OBUF_GTS_TRI_2_INV ));
    X_FF \DEC_Q_reg<1>/$1I11/FF  (.IN (DEC_Q109[1]), .CLK (n265), .CE (VCC), 
    .SET (GND), .RST (GSR), .OUT (\DEC_Q_reg[1]/$1I11/QINT ));
    X_BUF \DEC_Q_reg<1>/$1I11/OBUF  (.IN (\DEC_Q_reg[1]/$1I11/QINT ), .OUT 
    (\DEC_Q_reg[1]/$1I11/OBUF_GTS_TRI ));
    X_TRI \DEC_Q_reg<1>/$1I11/OBUF_GTS_TRI_106  (.IN 
    (\DEC_Q_reg[1]/$1I11/OBUF_GTS_TRI ), .OUT (DEC_Q[1]), .CTL 
    (\DEC_Q_reg[1]/$1I11/OBUF_GTS_TRI_2_INV ));
    X_FF \DEC_Q_reg<0>/$1I11/FF  (.IN (DEC_Q109[0]), .CLK (n265), .CE (VCC), 
    .SET (GND), .RST (GSR), .OUT (\DEC_Q_reg[0]/$1I11/QINT ));
    X_BUF \DEC_Q_reg<0>/$1I11/OBUF  (.IN (\DEC_Q_reg[0]/$1I11/QINT ), .OUT 
    (\DEC_Q_reg[0]/$1I11/OBUF_GTS_TRI ));
    X_TRI \DEC_Q_reg<0>/$1I11/OBUF_GTS_TRI_107  (.IN 
    (\DEC_Q_reg[0]/$1I11/OBUF_GTS_TRI ), .OUT (DEC_Q[0]), .CTL 
    (\DEC_Q_reg[0]/$1I11/OBUF_GTS_TRI_2_INV ));
    X_CKBUF \U131/clkbuf  (.IN (\U131/clkio_bufsig ), .OUT (n265));
    X_BUF \U131/clkio_buf  (.IN (CLK), .OUT (\U131/clkio_bufsig ));
    X_AND2 \U136/n339/2_0  (.IN0 (n310), .IN1 (n309), .OUT (\U136/2_0 ));
    X_AND2 \U136/n339  (.IN0 (\U136/2_0 ), .IN1 (n334), .OUT (\U136/n339_2_INV )
    );
    X_OR2 \U147/n310/2_0  (.IN0 (n342), .IN1 (n341), .OUT (\U147/2_0 ));
    X_OR2 \U147/n310/2_1  (.IN0 (n261), .IN1 (n258), .OUT (\U147/2_1 ));
    X_OR2 \U147/n310  (.IN0 (\U147/2_0 ), .IN1 (\U147/2_1 ), .OUT 
    (\U147/n310_2_INV ));
    X_OR2 \U149/n309/2_0  (.IN0 (n343), .IN1 (n256), .OUT (\U149/2_0 ));
    X_OR2 \U149/n309  (.IN0 (\U149/2_0 ), .IN1 (n257), .OUT (\U149/n309_2_INV )
    );
    X_INV U140_2_INV_108 (.IN (U140_2_INV), .OUT (DEC_Q109[4]));
    X_INV U142_2_INV_109 (.IN (U142_2_INV), .OUT (DEC_Q109[0]));
    X_INV U152_2_INV_110 (.IN (U152_2_INV), .OUT (n345));
    X_INV U157_2_INV_111 (.IN (U157_2_INV), .OUT (n311));
    X_INV \U136/n339_2_INV_112  (.IN (\U136/n339_2_INV ), .OUT (n339));
    X_INV \U147/n310_2_INV_113  (.IN (\U147/n310_2_INV ), .OUT (n310));
    X_INV \U149/n309_2_INV_114  (.IN (\U149/n309_2_INV ), .OUT (n309));
    X_INV \DEC_Q_reg<5>/$1I11/OBUF_GTS_TRI_2_INV_115  (.IN (GTS), .OUT 
    (\DEC_Q_reg[5]/$1I11/OBUF_GTS_TRI_2_INV ));
    X_INV \DEC_Q_reg<4>/$1I11/OBUF_GTS_TRI_2_INV_116  (.IN (GTS), .OUT 
    (\DEC_Q_reg[4]/$1I11/OBUF_GTS_TRI_2_INV ));
    X_INV \DEC_Q_reg<3>/$1I11/OBUF_GTS_TRI_2_INV_117  (.IN (GTS), .OUT 
    (\DEC_Q_reg[3]/$1I11/OBUF_GTS_TRI_2_INV ));
    X_INV \DEC_Q_reg<2>/$1I11/OBUF_GTS_TRI_2_INV_118  (.IN (GTS), .OUT 
    (\DEC_Q_reg[2]/$1I11/OBUF_GTS_TRI_2_INV ));
    X_INV \DEC_Q_reg<1>/$1I11/OBUF_GTS_TRI_2_INV_119  (.IN (GTS), .OUT 
    (\DEC_Q_reg[1]/$1I11/OBUF_GTS_TRI_2_INV ));
    X_INV \DEC_Q_reg<0>/$1I11/OBUF_GTS_TRI_2_INV_120  (.IN (GTS), .OUT 
    (\DEC_Q_reg[0]/$1I11/OBUF_GTS_TRI_2_INV ));
    X_ONE VCC_121 (.OUT (VCC));
    X_ZERO GND_122 (.OUT (GND));
    X_PD NGD2VER_PD_84 (.OUT (GSR) );
    X_PD NGD2VER_PD_85 (.OUT (GTS) );
  endmodule