time_sim.sdf

实用的程序代码

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "if_case")
  (DATE "Tue Jan  6 18:22:04 1998")
  (VENDOR "Xilinx")
  (PROGRAM "Xilinx VERILOG SDF writer")
  (VERSION "M1.4.12")
  (DIVIDER /)
  (VOLTAGE 5.00:5.00:5.00)
  (PROCESS)
  (TEMPERATURE 25.00:25.00:25.00)
  (TIMESCALE 1ps)
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    (INSTANCE U141)
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    (INSTANCE U144)
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      (ABSOLUTE
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    (CELLTYPE "X_OR2")
    (INSTANCE U158)
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      (ABSOLUTE
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        (IOPATH IN1 OUT  (0:0:0) (0:0:0))
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    (CELLTYPE "X_INV")
    (INSTANCE U160)
    (DELAY
      (ABSOLUTE
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    (CELLTYPE "X_OR2")
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      (ABSOLUTE
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    (INSTANCE U164)
    (DELAY
      (ABSOLUTE
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        (IOPATH IN1 OUT  (0:0:0) (0:0:0))
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  )
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    (CELLTYPE "X_AND2")
    (INSTANCE U165)
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      (ABSOLUTE
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        (IOPATH IN1 OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U166)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (0:0:0) (0:0:0))
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        (PORT IN1  (1466:1466:1466) (1466:1466:1466))
        (IOPATH IN1 OUT  (1600:1600:1600) (1600:1600:1600))
      )
    )
  )
  (CELL
    (CELLTYPE "X_XOR2")
    (INSTANCE U167)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (0:0:0) (0:0:0))
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        (IOPATH IN1 OUT  (0:0:0) (0:0:0))
      )
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  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U168)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (0:0:0) (0:0:0))
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        (PORT IN1  (2546:2546:2546) (2546:2546:2546))
        (IOPATH IN1 OUT  (1130:1130:1130) (1130:1130:1130))
      )
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    (INSTANCE U169)
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      (ABSOLUTE
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      )
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  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE DEC_Q_reg\<5\>\/\$1I11\/FF)
    (DELAY
      (ABSOLUTE
        (PORT IN  (4800:4800:4800) (4800:4800:4800))
        (PORT CLK  (1261:1261:1261) (1261:1261:1261))
        (IOPATH CLK OUT  (7030:7030:7030) (7030:7030:7030))
        (IOPATH SET OUT  (7030:7030:7030) (7030:7030:7030))
        (PORT RST  (1970:1970:1970) (1970:1970:1970))
        (IOPATH RST OUT  (7030:7030:7030) (7030:7030:7030))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (SETUP IN (posedge CLK) (0:0:0))
      (HOLD CE (posedge CLK) (500:500:500))
      (HOLD IN (posedge CLK) (0:0:0))
    )
  )
  (CELL
    (CELLTYPE "X_BUF")
    (INSTANCE DEC_Q_reg\<5\>\/\$1I11\/OBUF)
    (DELAY
      (ABSOLUTE
        (PORT IN  (0:0:0) (0:0:0))
        (IOPATH IN OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_TRI")
    (INSTANCE DEC_Q_reg\<5\>\/\$1I11\/OBUF_GTS_TRI_97)
    (DELAY
      (ABSOLUTE
        (PORT IN  (0:0:0) (0:0:0))
        (IOPATH IN OUT  (0:0:0) (0:0:0))
        (IOPATH CTL OUT ( )  ( )  (0:0:0) (0:0:0) (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE DEC_Q_reg\<4\>\/\$1I11\/FF)
    (DELAY
      (ABSOLUTE
        (PORT IN  (5553:5553:5553) (5553:5553:5553))
        (PORT CLK  (1228:1228:1228) (1228:1228:1228))
        (IOPATH CLK OUT  (7030:7030:7030) (7030:7030:7030))
        (IOPATH SET OUT  (7030:7030:7030) (7030:7030:7030))
        (PORT RST  (1970:1970:1970) (1970:1970:1970))
        (IOPATH RST OUT  (7030:7030:7030) (7030:7030:7030))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (SETUP IN (posedge CLK) (0:0:0))
      (HOLD CE (posedge CLK) (500:500:500))
      (HOLD IN (posedge CLK) (0:0:0))
    )
  )
  (CELL
    (CELLTYPE "X_BUF")
    (INSTANCE DEC_Q_reg\<4\>\/\$1I11\/OBUF)
    (DELAY
      (ABSOLUTE
        (PORT IN  (0:0:0) (0:0:0))
        (IOPATH IN OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_TRI")
    (INSTANCE DEC_Q_reg\<4\>\/\$1I11\/OBUF_GTS_TRI_98)
    (DELAY
      (ABSOLUTE
        (PORT IN  (0:0:0) (0:0:0))
        (IOPATH IN OUT  (0:0:0) (0:0:0))
        (IOPATH CTL OUT ( )  ( )  (0:0:0) (0:0:0) (0:0:0) (0:0:0))
      )
    )