time_sim.v

实用的程序代码

// Xilinx Verilog produced by program ngd2ver, Version M1.4.12
// Date: Tue Jan  6 18:22:04 1998
// Design file: time_sim.nga
// Device: 4005epc84-2
`timescale 1 ns/1 ps
`uselib dir=/home/zeppelin2/tech_apps/m1_4.12/verilog/data libext=.vmd

  module if_case (RESET, CLK, ADDR_A, ADDR_B, ADDR_C, ADDR_D, DEC_Q);
    input RESET;
    input CLK;
    input [1:0] ADDR_A;
    input [1:0] ADDR_B;
    input [1:0] ADDR_C;
    input [1:0] ADDR_D;
    output [5:0] DEC_Q;

    wire n387, n388, n389, n390, n391, n392, n393, n394, n395, n396, n443, n442
    , n463, n462, n466, n464, n465, n467, n468, n470, n469, n439, n471, n472, 
    \DEC_Q_reg[5]/$1I11/QINT , \DEC_Q_reg[5]/$1I11/OBUF_GTS_TRI , 
    \DEC_Q_reg[4]/$1I11/QINT , \DEC_Q_reg[4]/$1I11/OBUF_GTS_TRI , 
    \DEC_Q_reg[3]/$1I11/QINT , \DEC_Q_reg[3]/$1I11/OBUF_GTS_TRI , 
    \DEC_Q_reg[2]/$1I11/QINT , \DEC_Q_reg[2]/$1I11/OBUF_GTS_TRI , 
    \DEC_Q_reg[1]/$1I11/QINT , \DEC_Q_reg[1]/$1I11/OBUF_GTS_TRI , 
    \DEC_Q_reg[0]/$1I11/QINT , \DEC_Q_reg[0]/$1I11/OBUF_GTS_TRI , 
    \U150/clkio_bufsig , \U151/2_0 , \U151/2_1 , \U155/2_0 , \U159/2_0 , 
    \U170/2_0 , U152_2_INV, U156_2_INV, \DEC_Q_reg[5]/$1I11/OBUF_GTS_TRI_2_INV 
    , \DEC_Q_reg[4]/$1I11/OBUF_GTS_TRI_2_INV , 
    \DEC_Q_reg[3]/$1I11/OBUF_GTS_TRI_2_INV , 
    \DEC_Q_reg[2]/$1I11/OBUF_GTS_TRI_2_INV , 
    \DEC_Q_reg[1]/$1I11/OBUF_GTS_TRI_2_INV , 
    \DEC_Q_reg[0]/$1I11/OBUF_GTS_TRI_2_INV , GND, VCC;
    wire [5:0] DEC_Q137;
    `ifdef GSR_SIGNAL
      wire GSR = `GSR_SIGNAL ;
    `else
      wire GSR ;
    `endif
    `ifdef GTS_SIGNAL
      wire GTS = `GTS_SIGNAL ;
    `else
      wire GTS ;
    `endif
    initial $sdf_annotate("time_sim.sdf");

    X_BUF U141 (.IN (ADDR_A[1]), .OUT (n387));
    X_BUF U142 (.IN (ADDR_A[0]), .OUT (n388));
    X_BUF U143 (.IN (ADDR_B[1]), .OUT (n389));
    X_BUF U144 (.IN (ADDR_B[0]), .OUT (n390));
    X_BUF U145 (.IN (ADDR_C[1]), .OUT (n391));
    X_BUF U146 (.IN (ADDR_C[0]), .OUT (n392));
    X_BUF U147 (.IN (ADDR_D[1]), .OUT (n393));
    X_BUF U148 (.IN (ADDR_D[0]), .OUT (n394));
    X_BUF U149 (.IN (RESET), .OUT (n395));
    X_OR2 U152 (.IN0 (n388), .IN1 (n387), .OUT (U152_2_INV));
    X_OR2 U153 (.IN0 (n387), .IN1 (n388), .OUT (n463));
    X_INV U154 (.IN (n390), .OUT (n462));
    X_AND2 U156 (.IN0 (n464), .IN1 (n389), .OUT (U156_2_INV));
    X_OR2 U157 (.IN0 (n390), .IN1 (n389), .OUT (n465));
    X_OR2 U158 (.IN0 (n442), .IN1 (n390), .OUT (n464));
    X_INV U160 (.IN (n387), .OUT (n467));
    X_OR2 U161 (.IN0 (n388), .IN1 (n467), .OUT (n468));
    X_AND2 U162 (.IN0 (n468), .IN1 (n395), .OUT (DEC_Q137[2]));
    X_AND2 U163 (.IN0 (n387), .IN1 (n395), .OUT (DEC_Q137[3]));
    X_XOR2 U164 (.IN0 (n469), .IN1 (n393), .OUT (n470));
    X_AND2 U165 (.IN0 (n439), .IN1 (n394), .OUT (n469));
    X_AND2 U166 (.IN0 (n470), .IN1 (n395), .OUT (DEC_Q137[5]));
    X_XOR2 U167 (.IN0 (n439), .IN1 (n394), .OUT (n471));
    X_AND2 U168 (.IN0 (n471), .IN1 (n395), .OUT (DEC_Q137[4]));
    X_INV U169 (.IN (n443), .OUT (n472));
    X_IPAD \ADDR_A<1>_PAD  (.PAD (ADDR_A[1]));
    X_IPAD \ADDR_A<0>_PAD  (.PAD (ADDR_A[0]));
    X_IPAD \ADDR_B<1>_PAD  (.PAD (ADDR_B[1]));
    X_IPAD \ADDR_B<0>_PAD  (.PAD (ADDR_B[0]));
    X_IPAD \ADDR_C<1>_PAD  (.PAD (ADDR_C[1]));
    X_IPAD \ADDR_C<0>_PAD  (.PAD (ADDR_C[0]));
    X_IPAD \ADDR_D<1>_PAD  (.PAD (ADDR_D[1]));
    X_IPAD \ADDR_D<0>_PAD  (.PAD (ADDR_D[0]));
    X_IPAD RESET_PAD (.PAD (RESET));
    X_IPAD CLK_PAD (.PAD (CLK));
    X_OPAD \DEC_Q<5>_PAD  (.PAD (DEC_Q[5]));
    X_OPAD \DEC_Q<4>_PAD  (.PAD (DEC_Q[4]));
    X_OPAD \DEC_Q<3>_PAD  (.PAD (DEC_Q[3]));
    X_OPAD \DEC_Q<2>_PAD  (.PAD (DEC_Q[2]));
    X_OPAD \DEC_Q<1>_PAD  (.PAD (DEC_Q[1]));
    X_OPAD \DEC_Q<0>_PAD  (.PAD (DEC_Q[0]));
    X_FF \DEC_Q_reg<5>/$1I11/FF  (.IN (DEC_Q137[5]), .CLK (n396), .CE (VCC), 
    .SET (GND), .RST (GSR), .OUT (\DEC_Q_reg[5]/$1I11/QINT ));
    X_BUF \DEC_Q_reg<5>/$1I11/OBUF  (.IN (\DEC_Q_reg[5]/$1I11/QINT ), .OUT 
    (\DEC_Q_reg[5]/$1I11/OBUF_GTS_TRI ));
    X_TRI \DEC_Q_reg<5>/$1I11/OBUF_GTS_TRI_97  (.IN 
    (\DEC_Q_reg[5]/$1I11/OBUF_GTS_TRI ), .OUT (DEC_Q[5]), .CTL 
    (\DEC_Q_reg[5]/$1I11/OBUF_GTS_TRI_2_INV ));
    X_FF \DEC_Q_reg<4>/$1I11/FF  (.IN (DEC_Q137[4]), .CLK (n396), .CE (VCC), 
    .SET (GND), .RST (GSR), .OUT (\DEC_Q_reg[4]/$1I11/QINT ));
    X_BUF \DEC_Q_reg<4>/$1I11/OBUF  (.IN (\DEC_Q_reg[4]/$1I11/QINT ), .OUT 
    (\DEC_Q_reg[4]/$1I11/OBUF_GTS_TRI ));
    X_TRI \DEC_Q_reg<4>/$1I11/OBUF_GTS_TRI_98  (.IN 
    (\DEC_Q_reg[4]/$1I11/OBUF_GTS_TRI ), .OUT (DEC_Q[4]), .CTL 
    (\DEC_Q_reg[4]/$1I11/OBUF_GTS_TRI_2_INV ));
    X_FF \DEC_Q_reg<3>/$1I11/FF  (.IN (DEC_Q137[3]), .CLK (n396), .CE (VCC), 
    .SET (GND), .RST (GSR), .OUT (\DEC_Q_reg[3]/$1I11/QINT ));
    X_BUF \DEC_Q_reg<3>/$1I11/OBUF  (.IN (\DEC_Q_reg[3]/$1I11/QINT ), .OUT 
    (\DEC_Q_reg[3]/$1I11/OBUF_GTS_TRI ));
    X_TRI \DEC_Q_reg<3>/$1I11/OBUF_GTS_TRI_99  (.IN 
    (\DEC_Q_reg[3]/$1I11/OBUF_GTS_TRI ), .OUT (DEC_Q[3]), .CTL 
    (\DEC_Q_reg[3]/$1I11/OBUF_GTS_TRI_2_INV ));
    X_FF \DEC_Q_reg<2>/$1I11/FF  (.IN (DEC_Q137[2]), .CLK (n396), .CE (VCC), 
    .SET (GND), .RST (GSR), .OUT (\DEC_Q_reg[2]/$1I11/QINT ));
    X_BUF \DEC_Q_reg<2>/$1I11/OBUF  (.IN (\DEC_Q_reg[2]/$1I11/QINT ), .OUT 
    (\DEC_Q_reg[2]/$1I11/OBUF_GTS_TRI ));
    X_TRI \DEC_Q_reg<2>/$1I11/OBUF_GTS_TRI_100  (.IN 
    (\DEC_Q_reg[2]/$1I11/OBUF_GTS_TRI ), .OUT (DEC_Q[2]), .CTL 
    (\DEC_Q_reg[2]/$1I11/OBUF_GTS_TRI_2_INV ));
    X_FF \DEC_Q_reg<1>/$1I11/FF  (.IN (DEC_Q137[1]), .CLK (n396), .CE (VCC), 
    .SET (GND), .RST (GSR), .OUT (\DEC_Q_reg[1]/$1I11/QINT ));
    X_BUF \DEC_Q_reg<1>/$1I11/OBUF  (.IN (\DEC_Q_reg[1]/$1I11/QINT ), .OUT 
    (\DEC_Q_reg[1]/$1I11/OBUF_GTS_TRI ));
    X_TRI \DEC_Q_reg<1>/$1I11/OBUF_GTS_TRI_101  (.IN 
    (\DEC_Q_reg[1]/$1I11/OBUF_GTS_TRI ), .OUT (DEC_Q[1]), .CTL 
    (\DEC_Q_reg[1]/$1I11/OBUF_GTS_TRI_2_INV ));
    X_FF \DEC_Q_reg<0>/$1I11/FF  (.IN (DEC_Q137[0]), .CLK (n396), .CE (VCC), 
    .SET (GND), .RST (GSR), .OUT (\DEC_Q_reg[0]/$1I11/QINT ));
    X_BUF \DEC_Q_reg<0>/$1I11/OBUF  (.IN (\DEC_Q_reg[0]/$1I11/QINT ), .OUT 
    (\DEC_Q_reg[0]/$1I11/OBUF_GTS_TRI ));
    X_TRI \DEC_Q_reg<0>/$1I11/OBUF_GTS_TRI_102  (.IN 
    (\DEC_Q_reg[0]/$1I11/OBUF_GTS_TRI ), .OUT (DEC_Q[0]), .CTL 
    (\DEC_Q_reg[0]/$1I11/OBUF_GTS_TRI_2_INV ));
    X_CKBUF \U150/clkbuf  (.IN (\U150/clkio_bufsig ), .OUT (n396));
    X_BUF \U150/clkio_buf  (.IN (CLK), .OUT (\U150/clkio_bufsig ));
    X_OR2 \U151/n443/2_0  (.IN0 (n387), .IN1 (n388), .OUT (\U151/2_0 ));
    X_OR2 \U151/n443/2_1  (.IN0 (n389), .IN1 (n392), .OUT (\U151/2_1 ));
    X_OR2 \U151/n443  (.IN0 (\U151/2_0 ), .IN1 (\U151/2_1 ), .OUT (n443));
    X_AND2 \U155/DEC_Q137<0>/2_0  (.IN0 (n463), .IN1 (n462), .OUT (\U155/2_0 ));
    X_AND2 \U155/DEC_Q137<0>  (.IN0 (\U155/2_0 ), .IN1 (n395), .OUT 
    (DEC_Q137[0]));
    X_AND2 \U159/DEC_Q137<1>/2_0  (.IN0 (n466), .IN1 (n465), .OUT (\U159/2_0 ));
    X_AND2 \U159/DEC_Q137<1>  (.IN0 (\U159/2_0 ), .IN1 (n395), .OUT 
    (DEC_Q137[1]));
    X_AND2 \U170/n439/2_0  (.IN0 (n391), .IN1 (n472), .OUT (\U170/2_0 ));
    X_AND2 \U170/n439  (.IN0 (\U170/2_0 ), .IN1 (n390), .OUT (n439));
    X_INV U152_2_INV_103 (.IN (U152_2_INV), .OUT (n442));
    X_INV U156_2_INV_104 (.IN (U156_2_INV), .OUT (n466));
    X_INV \DEC_Q_reg<5>/$1I11/OBUF_GTS_TRI_2_INV_105  (.IN (GTS), .OUT 
    (\DEC_Q_reg[5]/$1I11/OBUF_GTS_TRI_2_INV ));
    X_INV \DEC_Q_reg<4>/$1I11/OBUF_GTS_TRI_2_INV_106  (.IN (GTS), .OUT 
    (\DEC_Q_reg[4]/$1I11/OBUF_GTS_TRI_2_INV ));
    X_INV \DEC_Q_reg<3>/$1I11/OBUF_GTS_TRI_2_INV_107  (.IN (GTS), .OUT 
    (\DEC_Q_reg[3]/$1I11/OBUF_GTS_TRI_2_INV ));
    X_INV \DEC_Q_reg<2>/$1I11/OBUF_GTS_TRI_2_INV_108  (.IN (GTS), .OUT 
    (\DEC_Q_reg[2]/$1I11/OBUF_GTS_TRI_2_INV ));
    X_INV \DEC_Q_reg<1>/$1I11/OBUF_GTS_TRI_2_INV_109  (.IN (GTS), .OUT 
    (\DEC_Q_reg[1]/$1I11/OBUF_GTS_TRI_2_INV ));
    X_INV \DEC_Q_reg<0>/$1I11/OBUF_GTS_TRI_2_INV_110  (.IN (GTS), .OUT 
    (\DEC_Q_reg[0]/$1I11/OBUF_GTS_TRI_2_INV ));
    X_ONE VCC_111 (.OUT (VCC));
    X_ZERO GND_112 (.OUT (GND));
    X_PD NGD2VER_PD_74 (.OUT (GSR) );
    X_PD NGD2VER_PD_75 (.OUT (GTS) );
  endmodule