time_sim.tv

实用的程序代码

// VERILOG TestFixture Template produced by ngd2ver M1.4.12
// Design file: time_sim.nga
// Date:Tue Jan  6 18:22:04 1998

// ATTENTION: This file was created by NGD2VER and may therefore be overwritten
// by subsequent runs of NGD2VER. Xilinx recommends that you copy this file to
// a new name, or 'paste' this text into another file, to avoid accidental loss
// of data.

`timescale 1 ns/1 ps

module test;
  reg RESET;
  reg CLK;
  reg [1:0] ADDR_A;
  reg [1:0] ADDR_B;
  reg [1:0] ADDR_C;
  reg [1:0] ADDR_D;
  wire [5:0] DEC_Q;

  reg GSR;
  `define GSR_SIGNAL test.GSR

  reg GTS;
  `define GTS_SIGNAL test.GTS

  if_case uut ( .RESET (RESET) , .CLK (CLK) , .ADDR_A (ADDR_A) , .ADDR_B (ADDR_B) 
, .ADDR_C (ADDR_C) , .ADDR_D (ADDR_D) , .DEC_Q (DEC_Q) );

  initial begin
    $timeformat(-9,3,"ns",12);
    $shm_open("time_sim.shm");
    $shm_probe("AS");
  end

  initial begin
    $display("           T RCAAAAD ");
    $display("           i ELDDDDE ");
    $display("           m SKDDDDC ");
    $display("           e E RRRR_ ");
    $display("             T ____Q ");
    $display("               ABCD[ ");
    $display("               [[[[5 ");
    $display("               1111: ");
    $display("               ::::0 ");
    $display("               0000] ");
    $display("               ]]]]  ");
    $monitor("%t",$realtime,, RESET, CLK, "%h", ADDR_A, "%h", ADDR_B, "%h", ADDR_C, "%h", ADDR_D, "%h", DEC_Q );
  end

  initial begin
      `GSR_SIGNAL = 1;
      `GTS_SIGNAL = 0;
    #100
      `GSR_SIGNAL = 0;
      RESET = 0 ;
      CLK = 0 ;
      ADDR_A = 0 ;
      ADDR_B = 0 ;
      ADDR_C = 0 ;
      ADDR_D = 0 ;
    #1000 $stop;
    // #1000 $finish;
  end

endmodule