time_sim.vhd

实用的程序代码

      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_OUT , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_COUT0 : X_OR2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_CIN_AND , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CO_3 ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_AND_55 : X_AND2 
      port map ( I0 => VCC , I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C7 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_AND ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_XOR_56 : X_XOR2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_AND , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_XOR ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_XOR_57 : X_XOR2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_XOR , I1 => N258 
      , O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_XOR ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_AND_58 : X_AND2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C6 , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_XOR , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_AND ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR_59 : X_OR2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_AND , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_COUT0_AND_60 : X_AND2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CO_3 , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_COUT0_AND ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND_61 : X_AND2 
      port map ( I0 => N258 , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_COUT : X_OR2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_COUT0_AND , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CO_4 ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C0BUF : X_BUF 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C0 ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C1BUF : X_BUF 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C1 ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C2BUF : X_BUF 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C2 ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C3BUF : X_BUF 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C3 ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C4BUF : X_BUF 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C4 ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C5BUF : X_BUF 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C5 ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C6BUF : X_BUF 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C6 ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C7BUF : X_BUF 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C7 ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_X_ZERO : X_ZERO 
      port map ( O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ZERO ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_X_ONE : X_ONE 
      port map ( O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_ARG139_3_2_0 : X_XOR2 
      port map ( 
      I0 => SUB_59_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_ARG139_3_2_0_0_INV , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CO_3 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_2_0 ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_ARG139_3_Q : X_XOR2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_2_0 , I1 => N258 
      , O => ARG139(3) ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_ARG139_2_2_0 : X_XOR2 
      port map ( 
      I0 => SUB_59_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_ARG139_2_2_0_0_INV , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CO_2 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_2_0 ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_ARG139_2_Q : X_XOR2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_2_0 , I1 => N259 
      , O => ARG139(2) ) ;
    N261_DFF_OUT_FFX : X_FF 
      port map ( I => N261_F , CLK => N197 , CE => VCC , SET => GSR , 
      RST => GND , O => N261 ) ;
    N261_DFF_OUT_FFY : X_FF 
      port map ( I => N261_G , CLK => N197 , CE => VCC , SET => GSR , 
      RST => GND , O => N260 ) ;
    N261_FGBLOCK_G2MUX : X_BUF 
      port map ( I => N261_FGBLOCK_COUT0 , O => N261_FGBLOCK_1N8 ) ;
    N261_FGBLOCK_LUTRAM_CARRYBLK_A0BUF : X_BUF 
      port map ( I => N261 , O => N261_FGBLOCK_COUT0 ) ;
    N261_FGBLOCK_LUTRAM_CARRYBLK_A1BUF_62 : X_BUF 
      port map ( I => N260 , O => N261_FGBLOCK_LUTRAM_CARRYBLK_A1BUF ) ;
    N261_FGBLOCK_LUTRAM_CARRYBLK_OR1 : X_OR2 
      port map ( I0 => N261_FGBLOCK_LUTRAM_CARRYBLK_AND4 , 
      I1 => N261_FGBLOCK_LUTRAM_CARRYBLK_AND5 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CO_2 ) ;
    N261_FGBLOCK_LUTRAM_CARRYBLK_AND4_63 : X_AND2 
      port map ( I0 => N261_FGBLOCK_COUT0 , 
      I1 => N261_FGBLOCK_LUTRAM_CARRYBLK_XOR3 , 
      O => N261_FGBLOCK_LUTRAM_CARRYBLK_AND4 ) ;
    N261_FGBLOCK_LUTRAM_CARRYBLK_INV1_64 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_N20 , 
      O => N261_FGBLOCK_LUTRAM_CARRYBLK_INV1 ) ;
    N261_FGBLOCK_LUTRAM_CARRYBLK_AND5_65 : X_AND2 
      port map ( I0 => N261_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV , 
      I1 => N261_FGBLOCK_LUTRAM_CARRYBLK_A1BUF , 
      O => N261_FGBLOCK_LUTRAM_CARRYBLK_AND5 ) ;
    N261_FGBLOCK_LUTRAM_CARRYBLK_XOR3_66 : X_XOR2 
      port map ( I0 => N261_FGBLOCK_LUTRAM_CARRYBLK_INV1 , 
      I1 => N261_FGBLOCK_LUTRAM_CARRYBLK_A1BUF , 
      O => N261_FGBLOCK_LUTRAM_CARRYBLK_XOR3 ) ;
    N261_FGBLOCK_LUTRAM_FLUT_OBUF : X_INV 
      port map ( I => N261 , O => N261_F ) ;
    N261_FGBLOCK_LUTRAM_GLUT_XOR0 : X_XOR2 
      port map ( I0 => N261_FGBLOCK_LUTRAM_GLUT_XOR0_0_INV , I1 => N260 , 
      O => N261_G ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV_67 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C5 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV_68 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C4 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV_69 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_N19 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV_70 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C4 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV_71 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C0 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV_72 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV_73 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C3 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV_74 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV_75 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C6 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV_76 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV_77 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C5 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV_78 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C4 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV_79 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_N20 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV_80 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C4 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV_81 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C0 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV_82 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV_83 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C3 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV_84 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV_85 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C6 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV_86 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_ARG58_3_2_0_0_INV_87 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_N19 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_ARG58_3_2_0_0_INV ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_ARG58_2_2_0_0_INV_88 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_N19 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_ARG58_2_2_0_0_INV ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_ARG139_3_2_0_0_INV_89 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_N20 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_ARG139_3_2_0_0_INV ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_ARG139_2_2_0_0_INV_90 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_N20 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_ARG139_2_2_0_0_INV ) ;
    U93_1I20_GTS_TRI_2_INV_91 : X_INV 
      port map ( I => GTS , O => U93_1I20_GTS_TRI_2_INV ) ;
    U94_1I20_GTS_TRI_2_INV_92 : X_INV 
      port map ( I => GTS , O => U94_1I20_GTS_TRI_2_INV ) ;
    U95_1I20_GTS_TRI_2_INV_93 : X_INV 
      port map ( I => GTS , O => U95_1I20_GTS_TRI_2_INV ) ;
    U96_1I20_GTS_TRI_2_INV_94 : X_INV 
      port map ( I => GTS , O => U96_1I20_GTS_TRI_2_INV ) ;
    U97_1I20_GTS_TRI_2_INV_95 : X_INV 
      port map ( I => GTS , O => U97_1I20_GTS_TRI_2_INV ) ;
    U98_1I20_GTS_TRI_2_INV_96 : X_INV 
      port map ( I => GTS , O => U98_1I20_GTS_TRI_2_INV ) ;
    U99_1I20_GTS_TRI_2_INV_97 : X_INV 
      port map ( I => GTS , O => U99_1I20_GTS_TRI_2_INV ) ;
    U100_1I20_GTS_TRI_2_INV_98 : X_INV 
      port map ( I => GTS , O => U100_1I20_GTS_TRI_2_INV ) ;
    N257_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV_99 : X_INV 
      port map ( I => N257_FGBLOCK_LUTRAM_CARRYBLK_XOR3 , 
      O => N257_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV ) ;
    N261_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV_100 : X_INV 
      port map ( I => N261_FGBLOCK_LUTRAM_CARRYBLK_XOR3 , 
      O => N261_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV ) ;
    N261_FGBLOCK_LUTRAM_GLUT_XOR0_0_INV_101 : X_INV 
      port map ( I => N261_FGBLOCK_1N8 , 
      O => N261_FGBLOCK_LUTRAM_GLUT_XOR0_0_INV ) ;
    VCC_102 : X_ONE 
      port map ( O => VCC ) ;
    GND_103 : X_ZERO 
      port map ( O => GND ) ;
end STRUCTURE ;