time_sim.vhd

实用的程序代码

      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C5 , 
      I2 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_C_15 : X_AND3 
      port map ( I0 => N255 , I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C5 , 
      I2 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C4 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_C ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_OUT_16 : X_OR3 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B , 
      I2 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_C , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_OUT ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND_17 : X_AND2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C1 , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C0_AND_18 : X_AND2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C0 , 
      I1 => ADD_50_PLUS_PLUS_N19 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C0_AND ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_19 : X_OR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C0_AND , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_AND_20 : X_AND2 
      port map ( I0 => VCC , I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C7 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_AND ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_XOR_21 : X_XOR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_AND , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_XOR ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F1_XOR_22 : X_XOR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_XOR , I1 => N255 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F1_XOR ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND_23 : X_AND2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C2 , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C3_AND_24 : X_AND2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C3 , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F1_XOR , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C3_AND ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXB_OUT_25 : X_OR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C3_AND , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXB_OUT ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_CIN_AND_26 : X_AND2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CO_2 , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_CIN_AND ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND_27 : X_AND2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_OUT , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT0 : X_OR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_CIN_AND , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CO_3 ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_AND_28 : X_AND2 
      port map ( I0 => VCC , I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C7 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_AND ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_XOR_29 : X_XOR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_AND , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_XOR ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_XOR_30 : X_XOR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_XOR , I1 => N254 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_XOR ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_AND_31 : X_AND2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C6 , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_XOR , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_AND ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR_32 : X_OR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_AND , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT0_AND_33 : X_AND2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CO_3 , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT0_AND ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND_34 : X_AND2 
      port map ( I0 => N254 , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT : X_OR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT0_AND , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CO_4 ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C0BUF : X_BUF 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C0 ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C1BUF : X_BUF 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C1 ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C2BUF : X_BUF 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C2 ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C3BUF : X_BUF 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C3 ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C4BUF : X_BUF 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C4 ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C5BUF : X_BUF 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C5 ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C6BUF : X_BUF 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C6 ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C7BUF : X_BUF 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C7 ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_X_ZERO : X_ZERO 
      port map ( O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ZERO ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_X_ONE : X_ONE 
      port map ( O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_ARG58_3_2_0 : X_XOR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_ARG58_3_2_0_0_INV 
      , I1 => ADD_50_PLUS_PLUS_U6_S0_1_CO_3 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_2_0 ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_ARG58_3_Q : X_XOR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_2_0 , I1 => N254 , 
      O => ARG58(3) ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_ARG58_2_2_0 : X_XOR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_ARG58_2_2_0_0_INV 
      , I1 => ADD_50_PLUS_PLUS_U6_S0_1_CO_2 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_2_0 ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_ARG58_2_Q : X_XOR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_2_0 , I1 => N255 , 
      O => ARG58(2) ) ;
    N257_DFF_OUT_FFX : X_FF 
      port map ( I => N257_F , CLK => N197 , CE => VCC , SET => GND , 
      RST => GSR , O => N257 ) ;
    N257_DFF_OUT_FFY : X_FF 
      port map ( I => N257_G , CLK => N197 , CE => VCC , SET => GND , 
      RST => GSR , O => N256 ) ;
    N257_FGBLOCK_G2MUX : X_BUF 
      port map ( I => N257_FGBLOCK_COUT0 , O => N257_FGBLOCK_1N8 ) ;
    N257_FGBLOCK_LUTRAM_CARRYBLK_A0BUF : X_BUF 
      port map ( I => N257 , O => N257_FGBLOCK_COUT0 ) ;
    N257_FGBLOCK_LUTRAM_CARRYBLK_A1BUF_35 : X_BUF 
      port map ( I => N256 , O => N257_FGBLOCK_LUTRAM_CARRYBLK_A1BUF ) ;
    N257_FGBLOCK_LUTRAM_CARRYBLK_OR1 : X_OR2 
      port map ( I0 => N257_FGBLOCK_LUTRAM_CARRYBLK_AND4 , 
      I1 => N257_FGBLOCK_LUTRAM_CARRYBLK_AND5 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CO_2 ) ;
    N257_FGBLOCK_LUTRAM_CARRYBLK_AND4_36 : X_AND2 
      port map ( I0 => N257_FGBLOCK_COUT0 , 
      I1 => N257_FGBLOCK_LUTRAM_CARRYBLK_XOR3 , 
      O => N257_FGBLOCK_LUTRAM_CARRYBLK_AND4 ) ;
    N257_FGBLOCK_LUTRAM_CARRYBLK_INV1_37 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_N19 , 
      O => N257_FGBLOCK_LUTRAM_CARRYBLK_INV1 ) ;
    N257_FGBLOCK_LUTRAM_CARRYBLK_AND5_38 : X_AND2 
      port map ( I0 => N257_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV , 
      I1 => N257_FGBLOCK_LUTRAM_CARRYBLK_A1BUF , 
      O => N257_FGBLOCK_LUTRAM_CARRYBLK_AND5 ) ;
    N257_FGBLOCK_LUTRAM_CARRYBLK_XOR3_39 : X_XOR2 
      port map ( I0 => N257_FGBLOCK_LUTRAM_CARRYBLK_INV1 , 
      I1 => N257_FGBLOCK_LUTRAM_CARRYBLK_A1BUF , 
      O => N257_FGBLOCK_LUTRAM_CARRYBLK_XOR3 ) ;
    N257_FGBLOCK_LUTRAM_FLUT_OBUF : X_INV 
      port map ( I => N257 , O => N257_F ) ;
    N257_FGBLOCK_LUTRAM_GLUT_XOR0 : X_XOR2 
      port map ( I0 => N257_FGBLOCK_1N8 , I1 => N256 , O => N257_G ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_40 : X_AND3 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C7 , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV , 
      I2 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_41 : X_AND3 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C5 , 
      I2 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_C_42 : X_AND3 
      port map ( I0 => N259 , I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C5 , 
      I2 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C4 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_C ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_OUT_43 : X_OR3 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B , 
      I2 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_C , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_OUT ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND_44 : X_AND2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C1 , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C0_AND_45 : X_AND2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C0 , 
      I1 => SUB_59_MINUS_MINUS_N20 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C0_AND ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_46 : X_OR2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C0_AND , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_AND_47 : X_AND2 
      port map ( I0 => VCC , I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C7 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_AND ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_XOR_48 : X_XOR2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_AND , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_XOR ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F1_XOR_49 : X_XOR2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_XOR , I1 => N259 
      , O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F1_XOR ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND_50 : X_AND2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C2 , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C3_AND_51 : X_AND2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C3 , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F1_XOR , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C3_AND ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXB_OUT_52 : X_OR2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C3_AND , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXB_OUT ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_CIN_AND_53 : X_AND2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CO_2 , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_CIN_AND ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND_54 : X_AND2