active_low_gsr.twr

实用的程序代码

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Xilinx TRACE, Version M1.4.12
Copyright (c) 1995-1997 Xilinx, Inc.  All rights reserved.

Design file:              active_low_gsr.ncd
Physical constraint file: active_low_gsr.pcf
Device,speed:             xc4005e,-2 (x1_0.86  PRELIMINARY)
Report level:             summary report
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WARNING:bastw:172 - No timing constraints found, doing advanced analysis with
   offsets.

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Timing constraint: Default period analysis for net n197
 16 items analyzed, 0 timing errors detected.
 Minimum period is   9.591ns.
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================================================================================
Timing constraint: Default OFFSET OUT AFTER analysis for clock "n197"
 8 items analyzed, 0 timing errors detected.
 Maximum allowable offset is  15.890ns.
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================================================================================
Timing constraint: Default path analysis
 16 items analyzed, 0 timing errors detected.
 Maximum delay is  11.935ns.
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All constraints were met.


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 40 paths, 0 nets, and 23 connections (95.8% coverage)

Design statistics:
   Minimum period:   9.591ns (Maximum frequency: 104.264MHz)
   Maximum combinational path delay:  11.935ns
   Maximum output required time before clock:  15.890ns


Analysis completed Tue Jan  6 16:56:58 1998
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