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📄 map.mrp

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💻 MRP
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               Xilinx Mapping Report File for Design "use_gsr"          Copyright (c) 1995-1997 Xilinx, Inc.  All rights reserved.Design Information------------------Command Line   : map use_gsr.ngd -o map.ncd use_gsr.pcf Target Device  : x4005eTarget Package : pc84Target Speed   : -2Mapper Version : xc4000e -- M1.4.12Mapped Date    : Tue Jan  6 16:50:37 1998Design Summary--------------   Number of errors:        0   Number of warnings:      7   Number of CLBs:              4 out of   196    2%      CLB Flip Flops:       8      4 input LUTs:         8      3 input LUTs:         0   Number of bonded IOBs:      10 out of    61   16%      IOB Flops:            0      IOB Latches:          0   Number of global buffers:    1 out of     8   12%   Number of secondary CLKs:    1 out of     4   25%   Number of STARTUPs:          1Total equivalent gate count for design: 138Additional JTAG gate count for IOBs:    480Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - Design AttributesSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - Added LogicSection 7 - Expanded LogicSection 8 - Signal Cross-ReferenceSection 9 - Symbol Cross-ReferenceSection 10 - IOB PropertiesSection 11 - RPMsSection 12 - Guide ReportSection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:baste:24 - All of the external outputs in this design are using   slew-rate-limited output drivers.  The delay on speed critical outputs can be   dramatically reduced by designating them as fast outputs in the original   design.  Please see your vendor interface documentation for specific   information on how to do this within your design-entry tool.   Note: You should be careful not to designate too many outputs which switch   together as fast, because this can cause excessive ground bounce.  For more   information on this subject, please refer to the IOB switching characteristic   guidelines for the device you are using in the Programmable Logic Data Book.WARNING:x4kma:111 - All the logic for FMAP symbol   "sub_50/minus/minus/u6/S0_1/FMAP5_2_f" (output   signal=sub_50/minus/minus/u6/FUNC<4>) has been removed!  This may be caused   by key logic being trimmed.  Please consult the Removed Logic section of this   report to see if this is the case.WARNING:x4kma:111 - All the logic for FMAP symbol   "sub_50/minus/minus/u6/S0_1/FMAP6_2_g" (output   signal=sub_50/minus/minus/u6/FUNC<5>) has been removed!  This may be caused   by key logic being trimmed.  Please consult the Removed Logic section of this   report to see if this is the case.WARNING:x4kma:111 - All the logic for FMAP symbol   "add_41/plus/plus/u6/S0_1/FMAP5_2_f" (output   signal=add_41/plus/plus/u6/FUNC<4>) has been removed!  This may be caused by   key logic being trimmed.  Please consult the Removed Logic section of this   report to see if this is the case.WARNING:x4kma:111 - All the logic for FMAP symbol   "add_41/plus/plus/u6/S0_1/FMAP6_2_g" (output   signal=add_41/plus/plus/u6/FUNC<5>) has been removed!  This may be caused by   key logic being trimmed.  Please consult the Removed Logic section of this   report to see if this is the case.WARNING:x4kma:340 - Signal "n254" on pin A1 of HIERCY4_32 symbol   "add_41/plus/plus/u6/S0_1/CY4_1" (output   signal=add_41/plus/plus/u6/S0_1/CO_3) is not required by carry mode   INCDEC-F-CI.  The signal is being removed.  This carry component has been   mode-reduced.  The original carry mode was "INCDEC-FG-CI".WARNING:x4kma:340 - Signal "n258" on pin A1 of HIERCY4_32 symbol   "sub_50/minus/minus/u6/S0_1/CY4_1" (output   signal=sub_50/minus/minus/u6/S0_1/CO_3) is not required by carry mode   INCDEC-F-CI.  The signal is being removed.  This carry component has been   mode-reduced.  The original carry mode was "INCDEC-FG-CI".Section 3 - Design Attributes-----------------------------Section 4 - Removed Logic Summary---------------------------------  13 Block(s) trimmed   5 block(s) optimized away  13 signal(s) removedSection 5 - Removed Logic-------------------------Block "U1/ROC" (X_ZERO) removed due to optimization.Block "net11.ZERO" (X_ZERO) removed due to optimization.Block "net12.ZERO" (X_ZERO) removed due to optimization.Block "add_41/plus/plus/n19.ONE" (X_ONE) removed due to optimization.Block "sub_50/minus/minus/n20.ZERO" (X_ZERO) removed due to optimization.The trimmed logic report below shows the logic removed from your design due tosourceless or loadless signals, and VCC or ground connections.  If the removalof a signal or symbol results in the subsequent removal of an additional signalor symbol, the message explaining that second removal will be indented.  Thisindentation will be repeated as a chain of related logic is removed.To quickly locate the original cause for the removal of a chain of logic, lookabove the place where that logic is listed in the trimming report, then locatethe lines that are least indented (begin at the leftmost edge).The signal "U1/TOC" is loadless and has been removed. Loadless block "U1/TOC" (X_ZERO) removed.The trimmed logic reported below is either:   1. part of a cycle   2. part of disabled logic   3. a side-effect of other trimmed logicThe signal "add_41/plus/plus/grnd_sig" is unused and has been removed. Unused block "add_41/plus/plus/grnd_sig.ZERO" (X_ZERO) removed.The signal "sub_50/minus/minus/grnd_sig" is unused and has been removed. Unused block "sub_50/minus/minus/grnd_sig.ZERO" (X_ZERO) removed.The signal "add_41/plus/plus/u6/FUNC<5>" is unused and has been removed. Unused block"add_41/plus/plus/u6/S0_1/XOR5_G_SUM_2/add_41/plus/plus/u6/FUNC<5>" (X_XOR2)removed.  The signal "add_41/plus/plus/u6/FUNC<5>/2.0" is unused and has been removed.   Unused block"add_41/plus/plus/u6/S0_1/XOR5_G_SUM_2/add_41/plus/plus/u6/FUNC<5>/2.0" (X_XOR2)removed.    The signal "add_41/plus/plus/u6/S0_1/CO_5" is unused and has been removed.     Unused block "add_41/plus/plus/u6/S0_1/CY4_2" (HIERCY4_31) removed.The signal "add_41/plus/plus/u6/FUNC<4>" is unused and has been removed. Unused block"add_41/plus/plus/u6/S0_1/XOR4_F_SUM_2/add_41/plus/plus/u6/FUNC<4>" (X_XOR2)removed.  The signal "add_41/plus/plus/u6/FUNC<4>/2.0" is unused and has been removed.   Unused block"add_41/plus/plus/u6/S0_1/XOR4_F_SUM_2/add_41/plus/plus/u6/FUNC<4>/2.0" (X_XOR2)removed.The signal "sub_50/minus/minus/u6/FUNC<5>" is unused and has been removed. Unused block"sub_50/minus/minus/u6/S0_1/XOR5_G_SUM_2/sub_50/minus/minus/u6/FUNC<5>" (X_XOR2)removed.  The signal "sub_50/minus/minus/u6/FUNC<5>/2.0" is unused and has been removed.   Unused block"sub_50/minus/minus/u6/S0_1/XOR5_G_SUM_2/sub_50/minus/minus/u6/FUNC<5>/2.0"(X_XOR2) removed.    The signal "sub_50/minus/minus/u6/S0_1/CO_5" is unused and has been removed.     Unused block "sub_50/minus/minus/u6/S0_1/CY4_2" (HIERCY4_31) removed.The signal "sub_50/minus/minus/u6/FUNC<4>" is unused and has been removed. Unused block"sub_50/minus/minus/u6/S0_1/XOR4_F_SUM_2/sub_50/minus/minus/u6/FUNC<4>" (X_XOR2)removed.  The signal "sub_50/minus/minus/u6/FUNC<4>/2.0" is unused and has been removed.   Unused block"sub_50/minus/minus/u6/S0_1/XOR4_F_SUM_2/sub_50/minus/minus/u6/FUNC<4>/2.0"(X_XOR2) removed.Section 6 - Added Logic-----------------------Section 7 - Expanded Logic--------------------------To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUEand rerun MAP.Section 8 - Signal Cross-Reference----------------------------------To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUEand rerun MAP.Section 9 - Symbol Cross-Reference----------------------------------To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUEand rerun MAP.Section 10 - IOB Properties---------------------------"UPCNT<3>" (IOB) : SLEW=SLOW"UPCNT<2>" (IOB) : SLEW=SLOW"UPCNT<1>" (IOB) : SLEW=SLOW"UPCNT<0>" (IOB) : SLEW=SLOW"DNCNT<3>" (IOB) : SLEW=SLOW"DNCNT<2>" (IOB) : SLEW=SLOW"DNCNT<1>" (IOB) : SLEW=SLOW"DNCNT<0>" (IOB) : SLEW=SLOWSection 11 - RPMs-----------------Section 12 - Guide Report-------------------------Guide not run on this design.

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