time_sim.vhd

实用的程序代码

      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXB_OUT ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_CIN_AND_95 : X_AND2 
      port map ( I0 => VCC , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXB_OUT , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_CIN_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXC_AND_96 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXC_OUT , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXC_AND_1_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXC_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_COUT0 : X_OR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_CIN_AND , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXC_AND , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CO_1 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G1_AND_97 : X_AND2 
      port map ( I0 => VCC , I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C7 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G1_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G1_XOR_98 : X_XOR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G1_AND , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXA_OUT , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G1_XOR ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G4_XOR_99 : X_XOR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G1_XOR , I1 => N260 
      , O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G4_XOR ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_AND_100 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C6 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G4_XOR , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_OR_101 : X_OR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_OR_0_INV , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_AND , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_OR ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_COUT0_AND_102 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CO_1 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_OR , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_COUT0_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G4_AND_103 : X_AND2 
      port map ( I0 => N260 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G4_AND_1_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G4_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_COUT : X_OR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_COUT0_AND , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G4_AND , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CO_2 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_C0BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_ONE , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C0 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_C1BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C1 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_C2BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C2 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_C3BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C3 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_C4BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_ONE , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C4 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_C5BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_ONE , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C5 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_C6BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_ONE , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C6 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_C7BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C7 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_X_ZERO : X_ZERO 
      port map ( O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_ZERO ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_X_ONE : X_ONE 
      port map ( O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_ONE ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_ARG139_3_2_0 : X_XOR2 
      port map ( 
      I0 => SUB_40_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_ARG139_3_2_0_0_INV , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CO_3 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_2_0 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_ARG139_3_Q : X_XOR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_2_0 , I1 => N258 
      , O => ARG139(3) ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_ARG139_2_2_0 : X_XOR2 
      port map ( 
      I0 => SUB_40_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_ARG139_2_2_0_0_INV , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CO_2 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_2_0 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_ARG139_2_Q : X_XOR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_2_0 , I1 => N259 
      , O => ARG139(2) ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_XOR1_G_SUM_0_ARG139_1_2_0 : X_XOR2 
      port map ( 
      I0 => SUB_40_MINUS_MINUS_U6_S0_1_XOR1_G_SUM_0_ARG139_1_2_0_0_INV , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CO_1 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_XOR1_G_SUM_0_2_0 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_XOR1_G_SUM_0_ARG139_1_Q : X_XOR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_XOR1_G_SUM_0_2_0 , I1 => N260 
      , O => ARG139(1) ) ;
    U91_CLKBUF : X_CKBUF 
      port map ( I => U91_CLKIO_BUFSIG , O => N197 ) ;
    U91_CLKIO_BUF : X_BUF 
      port map ( I => CLOCK , O => U91_CLKIO_BUFSIG ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV_104 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C5 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV_105 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C4 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV_106 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_N19 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV_107 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C4 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV_108 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C0 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV_109 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV_110 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C3 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV_111 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV_112 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C6 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV_113 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_1_INV_114 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C5 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_1_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_2_INV_115 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C4 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_2_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_0_INV_116 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_N19 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_0_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_2_INV_117 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C4 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_2_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C1_AND_1_INV_118 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C0 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C1_AND_1_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_2_INV_119 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_2_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C2_AND_1_INV_120 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C3 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C2_AND_1_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND_1_INV_121 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXB_OUT , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND_1_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR_0_INV_122 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C6 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR_0_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_AND_1_INV_123 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_AND_1_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV_124 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C5 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV_125 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C4 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV_126 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_N20 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV_127 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C4 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV_128 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C0 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV_129 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV_130 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C3 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV_131 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV_132 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C6 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV_133 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_A_1_INV_134 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C5 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_A_1_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_A_2_INV_135 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C4 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_A_2_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_B_0_INV_136 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_N20 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_B_0_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_B_2_INV_137 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C4 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_B_2_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C1_AND_1_INV_138 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C0 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C1_AND_1_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_2_INV_139 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_2_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXA_OUT ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C2_AND_1_INV_140 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C3 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C2_AND_1_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXC_AND_1_INV_141 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXB_OUT , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXC_AND_1_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_OR_0_INV_142 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C6 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_OR_0_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G4_AND_1_INV_143 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_OR , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G4_AND_1_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_ARG58_3_2_0_0_INV_144 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_N19 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_ARG58_3_2_0_0_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_ARG58_2_2_0_0_INV_145 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_N19 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_ARG58_2_2_0_0_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_ARG58_1_2_0_0_INV_146 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_N19 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_ARG58_1_2_0_0_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_ARG139_3_2_0_0_INV_147 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_N20 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_ARG139_3_2_0_0_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_ARG139_2_2_0_0_INV_148 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_N20 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_ARG139_2_2_0_0_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_XOR1_G_SUM_0_ARG139_1_2_0_0_INV_149 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_N20 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_XOR1_G_SUM_0_ARG139_1_2_0_0_INV ) ;
    U93_1I20_GTS_TRI_2_INV_150 : X_INV 
      port map ( I => GTS , O => U93_1I20_GTS_TRI_2_INV ) ;
    U94_1I20_GTS_TRI_2_INV_151 : X_INV 
      port map ( I => GTS , O => U94_1I20_GTS_TRI_2_INV ) ;
    U95_1I20_GTS_TRI_2_INV_152 : X_INV 
      port map ( I => GTS , O => U95_1I20_GTS_TRI_2_INV ) ;
    U96_1I20_GTS_TRI_2_INV_153 : X_INV 
      port map ( I => GTS , O => U96_1I20_GTS_TRI_2_INV ) ;
    U97_1I20_GTS_TRI_2_INV_154 : X_INV 
      port map ( I => GTS , O => U97_1I20_GTS_TRI_2_INV ) ;
    U98_1I20_GTS_TRI_2_INV_155 : X_INV 
      port map ( I => GTS , O => U98_1I20_GTS_TRI_2_INV ) ;
    U99_1I20_GTS_TRI_2_INV_156 : X_INV 
      port map ( I => GTS , O => U99_1I20_GTS_TRI_2_INV ) ;
    U100_1I20_GTS_TRI_2_INV_157 : X_INV 
      port map ( I => GTS , O => U100_1I20_GTS_TRI_2_INV ) ;
    VCC_158 : X_ONE 
      port map ( O => VCC ) ;
    GND_159 : X_ZERO 
      port map ( O => GND ) ;
    ROC_NGD2VHDL : ROC 
      port map ( O => GSR ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;