time_sim.vhd

实用的程序代码

      port map ( I0 => VCC , I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXB_OUT 
      , O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_CIN_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND_52 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_OUT , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND_1_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_COUT0 : X_OR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_CIN_AND , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CO_1 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G1_AND_53 : X_AND2 
      port map ( I0 => VCC , I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C7 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G1_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G1_XOR_54 : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G1_AND , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G1_XOR ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_XOR_55 : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G1_XOR , I1 => N256 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_XOR ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_AND_56 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C6 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_XOR , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR_57 : X_OR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR_0_INV , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_AND , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_COUT0_AND_58 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CO_1 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_COUT0_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_AND_59 : X_AND2 
      port map ( I0 => N256 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_AND_1_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_COUT : X_OR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_COUT0_AND , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_AND , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CO_2 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_C0BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ONE , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C0 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_C1BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C1 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_C2BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C2 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_C3BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C3 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_C4BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ONE , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C4 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_C5BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ONE , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C5 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_C6BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ONE , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C6 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_C7BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C7 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_X_ZERO : X_ZERO 
      port map ( O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ZERO ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_X_ONE : X_ONE 
      port map ( O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ONE ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_ARG58_3_2_0 : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_ARG58_3_2_0_0_INV 
      , I1 => ADD_31_PLUS_PLUS_U6_S0_1_CO_3 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_2_0 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_ARG58_3_Q : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_2_0 , I1 => N254 , 
      O => ARG58(3) ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_ARG58_2_2_0 : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_ARG58_2_2_0_0_INV 
      , I1 => ADD_31_PLUS_PLUS_U6_S0_1_CO_2 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_2_0 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_ARG58_2_Q : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_2_0 , I1 => N255 , 
      O => ARG58(2) ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_ARG58_1_2_0 : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_ARG58_1_2_0_0_INV 
      , I1 => ADD_31_PLUS_PLUS_U6_S0_1_CO_1 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_2_0 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_ARG58_1_Q : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_2_0 , I1 => N256 , 
      O => ARG58(1) ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_INV1_F_SUM_0 : X_INV 
      port map ( I => N261 , O => ARG139(0) ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_60 : X_AND3 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C7 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV , 
      I2 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_61 : X_AND3 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C5 , 
      I2 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_C_62 : X_AND3 
      port map ( I0 => N259 , I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C5 , 
      I2 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C4 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_C ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_OUT_63 : X_OR3 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B , 
      I2 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_C , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_OUT ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND_64 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C1 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C0_AND_65 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C0 , 
      I1 => SUB_40_MINUS_MINUS_N20 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C0_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_66 : X_OR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C0_AND , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_AND_67 : X_AND2 
      port map ( I0 => VCC , I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C7 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_XOR_68 : X_XOR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_AND , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_XOR ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F1_XOR_69 : X_XOR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_XOR , I1 => N259 
      , O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F1_XOR ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND_70 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C2 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C3_AND_71 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C3 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F1_XOR , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C3_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXB_OUT_72 : X_OR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C3_AND , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXB_OUT ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_CIN_AND_73 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CO_2 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_CIN_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND_74 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_OUT , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_COUT0 : X_OR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_CIN_AND , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CO_3 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_AND_75 : X_AND2 
      port map ( I0 => VCC , I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C7 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_XOR_76 : X_XOR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_AND , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_XOR ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_XOR_77 : X_XOR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_XOR , I1 => N258 
      , O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_XOR ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_AND_78 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C6 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_XOR , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR_79 : X_OR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_AND , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_COUT0_AND_80 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CO_3 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_COUT0_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND_81 : X_AND2 
      port map ( I0 => N258 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_COUT : X_OR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_COUT0_AND , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CO_4 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C0BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C0 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C1BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C1 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C2BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C2 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C3BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C3 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C4BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C4 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C5BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C5 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C6BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C6 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C7BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C7 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_X_ZERO : X_ZERO 
      port map ( O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ZERO ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_X_ONE : X_ONE 
      port map ( O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_A_82 : X_AND3 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C7 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_A_1_INV , 
      I2 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_A_2_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_A ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_B_83 : X_AND3 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_B_0_INV , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C5 , 
      I2 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_B_2_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_B ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_C_84 : X_AND3 
      port map ( I0 => N261 , I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C5 , 
      I2 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C4 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_C ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXC_OUT_85 : X_OR3 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_A , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_B , 
      I2 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_C , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXC_OUT ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C1_AND_86 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C1 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C1_AND_1_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C1_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C0_AND_87 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C0 , 
      I1 => SUB_40_MINUS_MINUS_N20 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C0_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_88 : X_OR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C0_AND , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C1_AND , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_2_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_F2_AND_89 : X_AND2 
      port map ( I0 => VCC , I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C7 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_F2_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_F2_XOR_90 : X_XOR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_F2_AND , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXA_OUT , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_F2_XOR ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_F1_XOR_91 : X_XOR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_F2_XOR , I1 => N261 
      , O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_F1_XOR ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C2_AND_92 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C2 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C2_AND_1_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C2_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C3_AND_93 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C3 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_F1_XOR , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C3_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXB_OUT_94 : X_OR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C2_AND , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C3_AND ,