time_sim.vhd

实用的程序代码

  begin
    U92 : X_BUF 
      port map ( I => RESET , O => N198 ) ;
    ADD_31_PLUS_PLUS_N19_ONE : X_ONE 
      port map ( O => ADD_31_PLUS_PLUS_N19 ) ;
    SUB_40_MINUS_MINUS_N20_ZERO : X_ZERO 
      port map ( O => SUB_40_MINUS_MINUS_N20 ) ;
    U93_1I20 : X_BUF 
      port map ( I => N254 , O => U93_1I20_GTS_TRI ) ;
    U93_1I20_GTS_TRI_0 : X_TRI 
      port map ( I => U93_1I20_GTS_TRI , O => UPCNT(3) , 
      CTL => U93_1I20_GTS_TRI_2_INV ) ;
    U94_1I20 : X_BUF 
      port map ( I => N255 , O => U94_1I20_GTS_TRI ) ;
    U94_1I20_GTS_TRI_1 : X_TRI 
      port map ( I => U94_1I20_GTS_TRI , O => UPCNT(2) , 
      CTL => U94_1I20_GTS_TRI_2_INV ) ;
    U95_1I20 : X_BUF 
      port map ( I => N256 , O => U95_1I20_GTS_TRI ) ;
    U95_1I20_GTS_TRI_2 : X_TRI 
      port map ( I => U95_1I20_GTS_TRI , O => UPCNT(1) , 
      CTL => U95_1I20_GTS_TRI_2_INV ) ;
    U96_1I20 : X_BUF 
      port map ( I => N257 , O => U96_1I20_GTS_TRI ) ;
    U96_1I20_GTS_TRI_3 : X_TRI 
      port map ( I => U96_1I20_GTS_TRI , O => UPCNT(0) , 
      CTL => U96_1I20_GTS_TRI_2_INV ) ;
    U97_1I20 : X_BUF 
      port map ( I => N258 , O => U97_1I20_GTS_TRI ) ;
    U97_1I20_GTS_TRI_4 : X_TRI 
      port map ( I => U97_1I20_GTS_TRI , O => DNCNT(3) , 
      CTL => U97_1I20_GTS_TRI_2_INV ) ;
    U98_1I20 : X_BUF 
      port map ( I => N259 , O => U98_1I20_GTS_TRI ) ;
    U98_1I20_GTS_TRI_5 : X_TRI 
      port map ( I => U98_1I20_GTS_TRI , O => DNCNT(2) , 
      CTL => U98_1I20_GTS_TRI_2_INV ) ;
    U99_1I20 : X_BUF 
      port map ( I => N260 , O => U99_1I20_GTS_TRI ) ;
    U99_1I20_GTS_TRI_6 : X_TRI 
      port map ( I => U99_1I20_GTS_TRI , O => DNCNT(1) , 
      CTL => U99_1I20_GTS_TRI_2_INV ) ;
    U100_1I20 : X_BUF 
      port map ( I => N261 , O => U100_1I20_GTS_TRI ) ;
    U100_1I20_GTS_TRI_7 : X_TRI 
      port map ( I => U100_1I20_GTS_TRI , O => DNCNT(0) , 
      CTL => U100_1I20_GTS_TRI_2_INV ) ;
    UP_CNT_REG_2_1I13 : X_FF 
      port map ( I => ARG58(2) , CLK => N197 , CE => VCC , SET => GND , 
      RST => UP_CNT_REG_2_1I13_GSR_OR , O => N255 ) ;
    UP_CNT_REG_2_1I13_GSR_OR_8 : X_OR2 
      port map ( I0 => N198 , I1 => GSR , O => UP_CNT_REG_2_1I13_GSR_OR ) ;
    UP_CNT_REG_3_1I13 : X_FF 
      port map ( I => ARG58(3) , CLK => N197 , CE => VCC , SET => GND , 
      RST => UP_CNT_REG_3_1I13_GSR_OR , O => N254 ) ;
    UP_CNT_REG_3_1I13_GSR_OR_9 : X_OR2 
      port map ( I0 => N198 , I1 => GSR , O => UP_CNT_REG_3_1I13_GSR_OR ) ;
    UP_CNT_REG_0_1I13 : X_FF 
      port map ( I => ARG58(0) , CLK => N197 , CE => VCC , SET => GND , 
      RST => UP_CNT_REG_0_1I13_GSR_OR , O => N257 ) ;
    UP_CNT_REG_0_1I13_GSR_OR_10 : X_OR2 
      port map ( I0 => N198 , I1 => GSR , O => UP_CNT_REG_0_1I13_GSR_OR ) ;
    UP_CNT_REG_1_1I13 : X_FF 
      port map ( I => ARG58(1) , CLK => N197 , CE => VCC , SET => GND , 
      RST => UP_CNT_REG_1_1I13_GSR_OR , O => N256 ) ;
    UP_CNT_REG_1_1I13_GSR_OR_11 : X_OR2 
      port map ( I0 => N198 , I1 => GSR , O => UP_CNT_REG_1_1I13_GSR_OR ) ;
    DN_CNT_REG_2_1I13 : X_FF 
      port map ( I => ARG139(2) , CLK => N197 , CE => VCC , 
      SET => DN_CNT_REG_2_1I13_GSR_OR , RST => GND , O => N259 ) ;
    DN_CNT_REG_2_1I13_GSR_OR_12 : X_OR2 
      port map ( I0 => N198 , I1 => GSR , O => DN_CNT_REG_2_1I13_GSR_OR ) ;
    DN_CNT_REG_3_1I13 : X_FF 
      port map ( I => ARG139(3) , CLK => N197 , CE => VCC , 
      SET => DN_CNT_REG_3_1I13_GSR_OR , RST => GND , O => N258 ) ;
    DN_CNT_REG_3_1I13_GSR_OR_13 : X_OR2 
      port map ( I0 => N198 , I1 => GSR , O => DN_CNT_REG_3_1I13_GSR_OR ) ;
    DN_CNT_REG_0_1I13 : X_FF 
      port map ( I => ARG139(0) , CLK => N197 , CE => VCC , 
      SET => DN_CNT_REG_0_1I13_GSR_OR , RST => GND , O => N261 ) ;
    DN_CNT_REG_0_1I13_GSR_OR_14 : X_OR2 
      port map ( I0 => N198 , I1 => GSR , O => DN_CNT_REG_0_1I13_GSR_OR ) ;
    DN_CNT_REG_1_1I13 : X_FF 
      port map ( I => ARG139(1) , CLK => N197 , CE => VCC , 
      SET => DN_CNT_REG_1_1I13_GSR_OR , RST => GND , O => N260 ) ;
    DN_CNT_REG_1_1I13_GSR_OR_15 : X_OR2 
      port map ( I0 => N198 , I1 => GSR , O => DN_CNT_REG_1_1I13_GSR_OR ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_INV1_F_SUM_0 : X_INV 
      port map ( I => N257 , O => ARG58(0) ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_16 : X_AND3 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C7 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV , 
      I2 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_17 : X_AND3 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C5 , 
      I2 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_C_18 : X_AND3 
      port map ( I0 => N255 , I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C5 , 
      I2 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C4 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_C ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_OUT_19 : X_OR3 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B , 
      I2 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_C , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_OUT ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND_20 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C1 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C0_AND_21 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C0 , 
      I1 => ADD_31_PLUS_PLUS_N19 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C0_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_22 : X_OR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C0_AND , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_AND_23 : X_AND2 
      port map ( I0 => VCC , I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C7 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_XOR_24 : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_AND , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_XOR ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F1_XOR_25 : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_XOR , I1 => N255 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F1_XOR ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND_26 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C2 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C3_AND_27 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C3 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F1_XOR , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C3_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXB_OUT_28 : X_OR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C3_AND , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXB_OUT ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_CIN_AND_29 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CO_2 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_CIN_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND_30 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_OUT , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT0 : X_OR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_CIN_AND , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CO_3 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_AND_31 : X_AND2 
      port map ( I0 => VCC , I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C7 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_XOR_32 : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_AND , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_XOR ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_XOR_33 : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_XOR , I1 => N254 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_XOR ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_AND_34 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C6 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_XOR , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR_35 : X_OR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_AND , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT0_AND_36 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CO_3 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT0_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND_37 : X_AND2 
      port map ( I0 => N254 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT : X_OR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT0_AND , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CO_4 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C0BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C0 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C1BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C1 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C2BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C2 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C3BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C3 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C4BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C4 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C5BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C5 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C6BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C6 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C7BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C7 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_X_ZERO : X_ZERO 
      port map ( O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ZERO ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_X_ONE : X_ONE 
      port map ( O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_38 : X_AND3 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C7 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_1_INV , 
      I2 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_2_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_39 : X_AND3 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_0_INV , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C5 , 
      I2 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_2_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_C_40 : X_AND3 
      port map ( I0 => N257 , I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C5 , 
      I2 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C4 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_C ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_OUT_41 : X_OR3 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B , 
      I2 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_C , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_OUT ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C1_AND_42 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C1 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C1_AND_1_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C1_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C0_AND_43 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C0 , 
      I1 => ADD_31_PLUS_PLUS_N19 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C0_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_44 : X_OR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C0_AND , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C1_AND , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_2_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F2_AND_45 : X_AND2 
      port map ( I0 => VCC , I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C7 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F2_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F2_XOR_46 : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F2_AND , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F2_XOR ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F1_XOR_47 : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F2_XOR , I1 => N257 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F1_XOR ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C2_AND_48 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C2 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C2_AND_1_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C2_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C3_AND_49 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C3 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F1_XOR , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C3_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXB_OUT_50 : X_OR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C2_AND , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C3_AND , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXB_OUT ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_CIN_AND_51 : X_AND2