time_sim.vhd

实用的程序代码

-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 16:54:22 1998
-- Design file: time_sim.nga
-- Device: 4005epc84-2
----- CELL ROC -----
-- Model for  Reset-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity ROC is
    generic ( InstancePath: STRING := "*";
              WIDTH : Time := 0 ns) ;
    port( O : out std_ulogic := '1' ) ;
    attribute VITAL_LEVEL0 of ROC : entity is TRUE ;
end ROC ;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      if (WIDTH <= 0 ns) then
         assert FALSE report
         "*** Error: a positive value of WIDTH must be specified ***"
         severity failure;
      else
         wait for WIDTH;
         O <= '0' ;
      end if;
      wait;
    end process ONE_SHOT ;
end ROC_V ;

configuration CFG_ROC_V of ROC is
    for ROC_V
    end for ;
end CFG_ROC_V ;
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity NO_GSR is
  port (
    CLOCK : in STD_LOGIC := 'X' ;
    RESET : in STD_LOGIC := 'X' ;
    UPCNT : out  STD_LOGIC_VECTOR ( 3 downto 0 );
    DNCNT : out  STD_LOGIC_VECTOR ( 3 downto 0 )
  ) ;
end NO_GSR ;

architecture STRUCTURE of NO_GSR is
  component ROC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal N197 , N198 , N254 , N255 , N256 , N257 , N258 , N259 , N260 , N261 , 
  ADD_31_PLUS_PLUS_N19 , SUB_40_MINUS_MINUS_N20 , U93_1I20_GTS_TRI , 
  U94_1I20_GTS_TRI , U95_1I20_GTS_TRI , U96_1I20_GTS_TRI , U97_1I20_GTS_TRI , 
  U98_1I20_GTS_TRI , U99_1I20_GTS_TRI , U100_1I20_GTS_TRI , 
  UP_CNT_REG_2_1I13_GSR_OR , UP_CNT_REG_3_1I13_GSR_OR , 
  UP_CNT_REG_0_1I13_GSR_OR , UP_CNT_REG_1_1I13_GSR_OR , 
  DN_CNT_REG_2_1I13_GSR_OR , DN_CNT_REG_3_1I13_GSR_OR , 
  DN_CNT_REG_0_1I13_GSR_OR , DN_CNT_REG_1_1I13_GSR_OR , 
  ADD_31_PLUS_PLUS_U6_S0_1_CO_4 , ADD_31_PLUS_PLUS_U6_S0_1_CO_3 , 
  ADD_31_PLUS_PLUS_U6_S0_1_CO_2 , ADD_31_PLUS_PLUS_U6_S0_1_CO_1 , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C0 , ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C1 , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C2 , ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C3 , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C4 , ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C5 , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C6 , ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C7 , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_C , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_OUT , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C0_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_XOR , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F1_XOR , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C3_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_CIN_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_XOR , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_XOR , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT0_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C0 , ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C1 , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C2 , ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C3 , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C4 , ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C5 , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C6 , ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C7 , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_C , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_OUT , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C1_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C0_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F2_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F2_XOR , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F1_XOR , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C2_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C3_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXB_OUT , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_CIN_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G1_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G1_XOR , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_XOR , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_COUT0_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ONE , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
  ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_2_0 , 
  ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_2_0 , 
  ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_2_0 , SUB_40_MINUS_MINUS_U6_S0_1_CO_4 , 
  SUB_40_MINUS_MINUS_U6_S0_1_CO_3 , SUB_40_MINUS_MINUS_U6_S0_1_CO_2 , 
  SUB_40_MINUS_MINUS_U6_S0_1_CO_1 , SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C0 , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C1 , SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C2 , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C3 , SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C4 , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C5 , SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C6 , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C7 , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_C , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_OUT , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C0_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_XOR , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F1_XOR , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C3_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_CIN_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_XOR , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_XOR , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_COUT0_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C0 , SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C1 , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C2 , SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C3 , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C4 , SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C5 , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C6 , SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C7 , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_A , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_B , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_C , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXC_OUT , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C1_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C0_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXA_OUT , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_F2_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_F2_XOR , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_F1_XOR , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C2_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C3_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXB_OUT , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_CIN_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXC_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G1_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G1_XOR , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G4_XOR , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_OR , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_COUT0_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G4_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_ONE , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
  SUB_40_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_2_0 , 
  SUB_40_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_2_0 , 
  SUB_40_MINUS_MINUS_U6_S0_1_XOR1_G_SUM_0_2_0 , U91_CLKIO_BUFSIG , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_1_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_2_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_0_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_2_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C1_AND_1_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_2_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C2_AND_1_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND_1_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR_0_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_AND_1_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_A_1_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_A_2_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_B_0_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_B_2_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C1_AND_1_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_2_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C2_AND_1_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXC_AND_1_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_OR_0_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G4_AND_1_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_ARG58_3_2_0_0_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_ARG58_2_2_0_0_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_ARG58_1_2_0_0_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_ARG139_3_2_0_0_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_ARG139_2_2_0_0_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_XOR1_G_SUM_0_ARG139_1_2_0_0_INV , 
  U93_1I20_GTS_TRI_2_INV , U94_1I20_GTS_TRI_2_INV , U95_1I20_GTS_TRI_2_INV , 
  U96_1I20_GTS_TRI_2_INV , U97_1I20_GTS_TRI_2_INV , U98_1I20_GTS_TRI_2_INV , 
  U99_1I20_GTS_TRI_2_INV , U100_1I20_GTS_TRI_2_INV , GND , GSR , VCC , GTS 
  : STD_LOGIC ;
  signal ARG58 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal ARG139 : STD_LOGIC_VECTOR ( 3 downto 0 );