time_sim.sdf

来自「实用的程序代码」· SDF 代码 · 共 2,476 行 · 第 1/4 页

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "no_gsr")
  (DATE "Tue Jan  6 18:57:43 1998")
  (VENDOR "Xilinx")
  (PROGRAM "Xilinx VERILOG SDF writer")
  (VERSION "M1.4.12")
  (DIVIDER /)
  (VOLTAGE 5.00:5.00:5.00)
  (PROCESS)
  (TEMPERATURE 25.00:25.00:25.00)
  (TIMESCALE 1ps)
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      (WIDTH (negedge CLK)  (4000:4000:4000))
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      (WIDTH (negedge CLK)  (4000:4000:4000))
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      (WIDTH (posedge RST)  (4000:4000:4000))
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      (WIDTH (negedge CLK)  (4000:4000:4000))
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