time_sim.tv

来自「实用的程序代码」· TV 代码 · 共 59 行

// VERILOG TestFixture Template produced by ngd2ver M1.4.12
// Design file: time_sim.nga
// Date:Tue Jan  6 18:57:43 1998

// ATTENTION: This file was created by NGD2VER and may therefore be overwritten
// by subsequent runs of NGD2VER. Xilinx recommends that you copy this file to
// a new name, or 'paste' this text into another file, to avoid accidental loss
// of data.

`timescale 1 ns/1 ps

module test;
  reg CLOCK;
  reg RESET;
  wire [3:0] UPCNT;
  wire [3:0] DNCNT;

  reg GSR;
  `define GSR_SIGNAL test.GSR

  reg GTS;
  `define GTS_SIGNAL test.GTS

  no_gsr uut ( .CLOCK (CLOCK) , .RESET (RESET) , .UPCNT (UPCNT) , .DNCNT (DNCNT) 
);

  initial begin
    $timeformat(-9,3,"ns",12);
    $shm_open("time_sim.shm");
    $shm_probe("AS");
  end

  initial begin
    $display("           T CRUD");
    $display("           i LEPN");
    $display("           m OSCC");
    $display("           e CENN");
    $display("             KTTT");
    $display("               [[");
    $display("               33");
    $display("               ::");
    $display("               00");
    $display("               ]]");
    $monitor("%t",$realtime,, CLOCK, RESET, "%h", UPCNT, "%h", DNCNT );
  end

  initial begin
      `GSR_SIGNAL = 1;
      `GTS_SIGNAL = 0;
    #100
      `GSR_SIGNAL = 0;
      CLOCK = 0 ;
      RESET = 0 ;
    #1000 $stop;
    // #1000 $finish;
  end

endmodule