time_sim.vhd

实用的程序代码

-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan 13 09:42:53 1998
-- Design file: time_sim.nga
-- Device: 4005epc84-2
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity XOR_SIG is
  port (
    B : in STD_LOGIC := 'X' ;
    C : in STD_LOGIC := 'X' ;
    X : out STD_LOGIC ;
    Y : out STD_LOGIC 
  ) ;
end XOR_SIG ;

architecture STRUCTURE of XOR_SIG is
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal N18 , N19 , N37 , U28_1I20_GTS_TRI , U29_1I20_GTS_TRI , 
  U28_1I20_GTS_TRI_2_INV , U29_1I20_GTS_TRI_2_INV , GTS : STD_LOGIC ;
  begin
    U26 : X_BUF 
      port map ( I => B , O => N18 ) ;
    U27 : X_BUF 
      port map ( I => C , O => N19 ) ;
    U30 : X_XOR2 
      port map ( I0 => N19 , I1 => N18 , O => N37 ) ;
    U28_1I20 : X_BUF 
      port map ( I => N37 , O => U28_1I20_GTS_TRI ) ;
    U28_1I20_GTS_TRI_0 : X_TRI 
      port map ( I => U28_1I20_GTS_TRI , O => X , CTL => U28_1I20_GTS_TRI_2_INV 
      ) ;
    U29_1I20 : X_BUF 
      port map ( I => N37 , O => U29_1I20_GTS_TRI ) ;
    U29_1I20_GTS_TRI_1 : X_TRI 
      port map ( I => U29_1I20_GTS_TRI , O => Y , CTL => U29_1I20_GTS_TRI_2_INV 
      ) ;
    U28_1I20_GTS_TRI_2_INV_2 : X_INV 
      port map ( I => GTS , O => U28_1I20_GTS_TRI_2_INV ) ;
    U29_1I20_GTS_TRI_2_INV_3 : X_INV 
      port map ( I => GTS , O => U29_1I20_GTS_TRI_2_INV ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;