time_sim.vhd

实用的程序代码

-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 16:00:43 1998
-- Design file: time_sim.nga
-- Device: 4005epc84-2
----- CELL ROC -----
-- Model for  Reset-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity ROC is
    generic ( InstancePath: STRING := "*";
              WIDTH : Time := 0 ns) ;
    port( O : out std_ulogic := '1' ) ;
    attribute VITAL_LEVEL0 of ROC : entity is TRUE ;
end ROC ;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      if (WIDTH <= 0 ns) then
         assert FALSE report
         "*** Error: a positive value of WIDTH must be specified ***"
         severity failure;
      else
         wait for WIDTH;
         O <= '0' ;
      end if;
      wait;
    end process ONE_SHOT ;
end ROC_V ;

configuration CFG_ROC_V of ROC is
    for ROC_V
    end for ;
end CFG_ROC_V ;
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity ENUM is
  port (
    CLOCK : in STD_LOGIC := 'X' ;
    RESET : in STD_LOGIC := 'X' ;
    A : in STD_LOGIC := 'X' ;
    B : in STD_LOGIC := 'X' ;
    C : in STD_LOGIC := 'X' ;
    D : in STD_LOGIC := 'X' ;
    E : in STD_LOGIC := 'X' ;
    SINGLE : out STD_LOGIC ;
    MULTI : out STD_LOGIC ;
    CONTIG : out STD_LOGIC 
  ) ;
end ENUM ;

architecture STRUCTURE of ENUM is
  component ROC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal N124 , N125 , N126 , N127 , N128 , N129 , N130 , U99_N58 , U99_N57 , 
  U99_N56 , U99_S2_Q , U99_S5_Q , U99_S4_Q , U99_N28 , U99_N29 , U99_N13 , 
  U99_N30 , U99_S1_Q , U99_N31 , U99_N14 , U99_N34 , U99_N33 , U99_N32 , 
  U99_S3_Q , U99_N35 , U99_N37 , U99_N36 , U99_N38 , U99_N40 , U99_N39 , 
  U99_S7_Q , U99_N43 , U99_N41 , U99_N42 , U99_N44 , U99_N46 , U99_N45 , 
  U99_N49 , U99_N47 , U99_N48 , U99_N51 , U99_N50 , U99_N55 , U99_N54 , U99_N53 
  , U99_N52 , U99_U36_1I20_GTS_TRI , U99_U37_1I20_GTS_TRI , 
  U99_U38_1I20_GTS_TRI , U99_S4_1I13_GSR_OR , U99_S6_1I13_GSR_OR , 
  U99_S5_1I13_GSR_OR , U99_S7_1I13_GSR_OR , U99_S2_1I13_GSR_OR , 
  U99_S3_1I13_GSR_OR , U99_S1_1I13_GSR_OR , U113_CLKIO_BUFSIG , U99_U39_2_0 , 
  U99_U43_2_0 , U99_U49_2_0 , U99_U53_2_0 , U99_U58_2_0 , U99_U58_2_1 , 
  U99_U64_2_0 , U99_U64_2_1 , U99_U41_2_INV , U99_U44_2_INV , U99_U45_2_INV , 
  U99_U47_2_INV , U99_U51_2_INV , U99_U56_2_INV , U99_U60_2_INV , U99_U62_2_INV 
  , U99_U66_2_INV , U99_U68_2_INV , U99_U53_U99_N56_2_INV , 
  U99_U36_1I20_GTS_TRI_2_INV , U99_U37_1I20_GTS_TRI_2_INV , 
  U99_U38_1I20_GTS_TRI_2_INV , GND , GSR , VCC , GTS : STD_LOGIC ;
  begin
    U114 : X_BUF 
      port map ( I => RESET , O => N125 ) ;
    U115 : X_BUF 
      port map ( I => A , O => N126 ) ;
    U116 : X_BUF 
      port map ( I => B , O => N127 ) ;
    U117 : X_BUF 
      port map ( I => C , O => N128 ) ;
    U118 : X_BUF 
      port map ( I => D , O => N129 ) ;
    U119 : X_BUF 
      port map ( I => E , O => N130 ) ;
    U99_U40 : X_INV 
      port map ( I => U99_S4_Q , O => U99_N28 ) ;
    U99_U41 : X_OR2 
      port map ( I0 => U99_N13 , I1 => U99_N28 , O => U99_U41_2_INV ) ;
    U99_U42 : X_AND2 
      port map ( I0 => U99_N13 , I1 => U99_S1_Q , O => U99_N30 ) ;
    U99_U44 : X_AND2 
      port map ( I0 => N129 , I1 => U99_S2_Q , O => U99_U44_2_INV ) ;
    U99_U45 : X_AND2 
      port map ( I0 => U99_N32 , I1 => U99_S3_Q , O => U99_U45_2_INV ) ;
    U99_U46 : X_OR2 
      port map ( I0 => N126 , I1 => N129 , O => U99_N32 ) ;
    U99_U47 : X_AND2 
      port map ( I0 => U99_N33 , I1 => U99_N34 , O => U99_U47_2_INV ) ;
    U99_U48 : X_INV 
      port map ( I => N128 , O => U99_N35 ) ;
    U99_U50 : X_INV 
      port map ( I => U99_N36 , O => U99_N37 ) ;
    U99_U51 : X_AND2 
      port map ( I0 => N130 , I1 => U99_N58 , O => U99_U51_2_INV ) ;
    U99_U52 : X_OR2 
      port map ( I0 => U99_S5_Q , I1 => U99_N37 , O => U99_N38 ) ;
    U99_U54 : X_INV 
      port map ( I => U99_N39 , O => U99_N40 ) ;
    U99_U55 : X_OR2 
      port map ( I0 => U99_N58 , I1 => U99_S7_Q , O => U99_N39 ) ;
    U99_U56 : X_OR2 
      port map ( I0 => U99_N40 , I1 => N130 , O => U99_U56_2_INV ) ;
    U99_U57 : X_INV 
      port map ( I => N128 , O => U99_N41 ) ;
    U99_U59 : X_INV 
      port map ( I => N126 , O => U99_N44 ) ;
    U99_U60 : X_OR2 
      port map ( I0 => U99_S2_Q , I1 => U99_N45 , O => U99_U60_2_INV ) ;
    U99_U61 : X_AND2 
      port map ( I0 => U99_N44 , I1 => U99_S3_Q , O => U99_N45 ) ;
    U99_U62 : X_OR2 
      port map ( I0 => U99_N46 , I1 => N129 , O => U99_U62_2_INV ) ;
    U99_U63 : X_INV 
      port map ( I => N127 , O => U99_N47 ) ;
    U99_U65 : X_INV 
      port map ( I => U99_N50 , O => U99_N51 ) ;
    U99_U66 : X_AND2 
      port map ( I0 => N130 , I1 => U99_S7_Q , O => U99_U66_2_INV ) ;
    U99_U67 : X_OR2 
      port map ( I0 => U99_N54 , I1 => U99_N51 , O => U99_N55 ) ;
    U99_U68 : X_AND2 
      port map ( I0 => N126 , I1 => U99_N52 , O => U99_U68_2_INV ) ;
    U99_U69 : X_XOR2 
      port map ( I0 => N128 , I1 => N127 , O => U99_N52 ) ;
    U99_U70 : X_AND2 
      port map ( I0 => U99_N53 , I1 => U99_S1_Q , O => U99_N54 ) ;
    U99_U36_1I20 : X_BUF 
      port map ( I => U99_N58 , O => U99_U36_1I20_GTS_TRI ) ;
    U99_U36_1I20_GTS_TRI_0 : X_TRI 
      port map ( I => U99_U36_1I20_GTS_TRI , O => SINGLE , 
      CTL => U99_U36_1I20_GTS_TRI_2_INV ) ;
    U99_U37_1I20 : X_BUF 
      port map ( I => U99_N57 , O => U99_U37_1I20_GTS_TRI ) ;
    U99_U37_1I20_GTS_TRI_1 : X_TRI 
      port map ( I => U99_U37_1I20_GTS_TRI , O => MULTI , 
      CTL => U99_U37_1I20_GTS_TRI_2_INV ) ;
    U99_U38_1I20 : X_BUF 
      port map ( I => U99_N56 , O => U99_U38_1I20_GTS_TRI ) ;
    U99_U38_1I20_GTS_TRI_2 : X_TRI 
      port map ( I => U99_U38_1I20_GTS_TRI , O => CONTIG , 
      CTL => U99_U38_1I20_GTS_TRI_2_INV ) ;
    U99_S4_1I13 : X_FF 
      port map ( I => U99_N31 , CLK => N124 , CE => VCC , SET => GND , 
      RST => U99_S4_1I13_GSR_OR , O => U99_S4_Q ) ;
    U99_S4_1I13_GSR_OR_3 : X_OR2 
      port map ( I0 => N125 , I1 => GSR , O => U99_S4_1I13_GSR_OR ) ;
    U99_S6_1I13 : X_FF 
      port map ( I => U99_N38 , CLK => N124 , CE => VCC , SET => GND , 
      RST => U99_S6_1I13_GSR_OR , O => U99_N58 ) ;
    U99_S6_1I13_GSR_OR_4 : X_OR2 
      port map ( I0 => N125 , I1 => GSR , O => U99_S6_1I13_GSR_OR ) ;
    U99_S5_1I13 : X_FF 
      port map ( I => U99_N42 , CLK => N124 , CE => VCC , SET => GND , 
      RST => U99_S5_1I13_GSR_OR , O => U99_S5_Q ) ;
    U99_S5_1I13_GSR_OR_5 : X_OR2 
      port map ( I0 => N125 , I1 => GSR , O => U99_S5_1I13_GSR_OR ) ;
    U99_S7_1I13 : X_FF 
      port map ( I => U99_N43 , CLK => N124 , CE => VCC , SET => GND , 
      RST => U99_S7_1I13_GSR_OR , O => U99_S7_Q ) ;
    U99_S7_1I13_GSR_OR_6 : X_OR2 
      port map ( I0 => N125 , I1 => GSR , O => U99_S7_1I13_GSR_OR ) ;
    U99_S2_1I13 : X_FF 
      port map ( I => U99_N48 , CLK => N124 , CE => VCC , SET => GND , 
      RST => U99_S2_1I13_GSR_OR , O => U99_S2_Q ) ;
    U99_S2_1I13_GSR_OR_7 : X_OR2 
      port map ( I0 => N125 , I1 => GSR , O => U99_S2_1I13_GSR_OR ) ;
    U99_S3_1I13 : X_FF 
      port map ( I => U99_N49 , CLK => N124 , CE => VCC , SET => GND , 
      RST => U99_S3_1I13_GSR_OR , O => U99_S3_Q ) ;
    U99_S3_1I13_GSR_OR_8 : X_OR2 
      port map ( I0 => N125 , I1 => GSR , O => U99_S3_1I13_GSR_OR ) ;
    U99_S1_1I13 : X_FF 
      port map ( I => U99_N55 , CLK => N124 , CE => VCC , 
      SET => U99_S1_1I13_GSR_OR , RST => GND , O => U99_S1_Q ) ;
    U99_S1_1I13_GSR_OR_9 : X_OR2 
      port map ( I0 => N125 , I1 => GSR , O => U99_S1_1I13_GSR_OR ) ;
    U113_CLKBUF : X_CKBUF 
      port map ( I => U113_CLKIO_BUFSIG , O => N124 ) ;
    U113_CLKIO_BUF : X_BUF 
      port map ( I => CLOCK , O => U113_CLKIO_BUFSIG ) ;
    U99_U39_U99_N57_2_0 : X_OR2 
      port map ( I0 => U99_S4_Q , I1 => U99_S5_Q , O => U99_U39_2_0 ) ;
    U99_U39_U99_N57 : X_OR2 
      port map ( I0 => U99_U39_2_0 , I1 => U99_S2_Q , O => U99_N57 ) ;
    U99_U43_U99_N31_2_0 : X_OR2 
      port map ( I0 => U99_N30 , I1 => U99_N29 , O => U99_U43_2_0 ) ;
    U99_U43_U99_N31 : X_OR2 
      port map ( I0 => U99_U43_2_0 , I1 => U99_N14 , O => U99_N31 ) ;
    U99_U49_U99_N13_2_0 : X_AND2 
      port map ( I0 => N126 , I1 => U99_N35 , O => U99_U49_2_0 ) ;
    U99_U49_U99_N13 : X_AND2 
      port map ( I0 => U99_U49_2_0 , I1 => N127 , O => U99_N13 ) ;
    U99_U53_U99_N56_2_0 : X_OR2 
      port map ( I0 => U99_S5_Q , I1 => U99_S1_Q , O => U99_U53_2_0 ) ;
    U99_U53_U99_N56 : X_OR2 
      port map ( I0 => U99_U53_2_0 , I1 => U99_S2_Q , 
      O => U99_U53_U99_N56_2_INV ) ;
    U99_U58_U99_N42_2_0 : X_AND2 
      port map ( I0 => U99_S4_Q , I1 => N127 , O => U99_U58_2_0 ) ;
    U99_U58_U99_N42_2_1 : X_AND2 
      port map ( I0 => N126 , I1 => U99_N41 , O => U99_U58_2_1 ) ;
    U99_U58_U99_N42 : X_AND2 
      port map ( I0 => U99_U58_2_0 , I1 => U99_U58_2_1 , O => U99_N42 ) ;
    U99_U64_U99_N48_2_0 : X_AND2 
      port map ( I0 => U99_S1_Q , I1 => N128 , O => U99_U64_2_0 ) ;
    U99_U64_U99_N48_2_1 : X_AND2 
      port map ( I0 => N126 , I1 => U99_N47 , O => U99_U64_2_1 ) ;
    U99_U64_U99_N48 : X_AND2 
      port map ( I0 => U99_U64_2_0 , I1 => U99_U64_2_1 , O => U99_N48 ) ;
    U99_U41_2_INV_10 : X_INV 
      port map ( I => U99_U41_2_INV , O => U99_N29 ) ;
    U99_U44_2_INV_11 : X_INV 
      port map ( I => U99_U44_2_INV , O => U99_N34 ) ;
    U99_U45_2_INV_12 : X_INV 
      port map ( I => U99_U45_2_INV , O => U99_N33 ) ;
    U99_U47_2_INV_13 : X_INV 
      port map ( I => U99_U47_2_INV , O => U99_N14 ) ;
    U99_U51_2_INV_14 : X_INV 
      port map ( I => U99_U51_2_INV , O => U99_N36 ) ;
    U99_U56_2_INV_15 : X_INV 
      port map ( I => U99_U56_2_INV , O => U99_N43 ) ;
    U99_U60_2_INV_16 : X_INV 
      port map ( I => U99_U60_2_INV , O => U99_N46 ) ;
    U99_U62_2_INV_17 : X_INV 
      port map ( I => U99_U62_2_INV , O => U99_N49 ) ;
    U99_U66_2_INV_18 : X_INV 
      port map ( I => U99_U66_2_INV , O => U99_N50 ) ;
    U99_U68_2_INV_19 : X_INV 
      port map ( I => U99_U68_2_INV , O => U99_N53 ) ;
    U99_U53_U99_N56_2_INV_20 : X_INV 
      port map ( I => U99_U53_U99_N56_2_INV , O => U99_N56 ) ;
    U99_U36_1I20_GTS_TRI_2_INV_21 : X_INV 
      port map ( I => GTS , O => U99_U36_1I20_GTS_TRI_2_INV ) ;
    U99_U37_1I20_GTS_TRI_2_INV_22 : X_INV 
      port map ( I => GTS , O => U99_U37_1I20_GTS_TRI_2_INV ) ;
    U99_U38_1I20_GTS_TRI_2_INV_23 : X_INV 
      port map ( I => GTS , O => U99_U38_1I20_GTS_TRI_2_INV ) ;
    VCC_24 : X_ONE 
      port map ( O => VCC ) ;
    GND_25 : X_ZERO 
      port map ( O => GND ) ;
    ROC_NGD2VHDL : ROC 
      port map ( O => GSR ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;