binary.twr

实用的程序代码

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Xilinx TRACE, Version M1.4.12
Copyright (c) 1995-1997 Xilinx, Inc.  All rights reserved.

Design file:              binary.ncd
Physical constraint file: binary.pcf
Device,speed:             xc4005e,-2 (x1_0.86  PRELIMINARY)
Report level:             summary report
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WARNING:bastw:172 - No timing constraints found, doing advanced analysis with
   offsets.

================================================================================
Timing constraint: Default period analysis for net n78
 54 items analyzed, 0 timing errors detected.
 Minimum period is  13.887ns.
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================================================================================
Timing constraint: Default OFFSET IN BEFORE analysis for clock "n78"
 25 items analyzed, 0 timing errors detected.
 Minimum allowable offset is   9.423ns.
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================================================================================
Timing constraint: Default OFFSET OUT AFTER analysis for clock "n78"
 9 items analyzed, 0 timing errors detected.
 Maximum allowable offset is  19.062ns.
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================================================================================
Timing constraint: Default path analysis
 12 items analyzed, 0 timing errors detected.
 Maximum delay is  15.114ns.
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All constraints were met.


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 95 paths, 0 nets, and 70 connections (100.0% coverage)

Design statistics:
   Minimum period:  13.887ns (Maximum frequency:  72.010MHz)
   Maximum combinational path delay:  15.114ns
   Minimum input arrival time before clock:   9.423ns
   Maximum output required time before clock:  19.062ns


Analysis completed Tue Jan  6 16:03:23 1998
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