enum.twr

来自「实用的程序代码」· TWR 代码 · 共 59 行

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--------------------------------------------------------------------------------Xilinx TRACE, Version M1.4.12Copyright (c) 1995-1997 Xilinx, Inc.  All rights reserved.Design file:              enum.ncdPhysical constraint file: enum.pcfDevice,speed:             xc4005e,-2 (x1_0.86  PRELIMINARY)Report level:             summary report--------------------------------------------------------------------------------WARNING:bastw:172 - No timing constraints found, doing advanced analysis with   offsets.================================================================================Timing constraint: Default period analysis for net n174 40 items analyzed, 0 timing errors detected. Minimum period is   9.938ns.--------------------------------------------------------------------------------================================================================================Timing constraint: Default OFFSET IN BEFORE analysis for clock "n174" 26 items analyzed, 0 timing errors detected. Minimum allowable offset is   5.656ns.--------------------------------------------------------------------------------================================================================================Timing constraint: Default OFFSET OUT AFTER analysis for clock "n174" 7 items analyzed, 0 timing errors detected. Maximum allowable offset is  18.840ns.--------------------------------------------------------------------------------================================================================================Timing constraint: Default path analysis 14 items analyzed, 0 timing errors detected. Maximum delay is  14.885ns.--------------------------------------------------------------------------------All constraints were met.Timing summary:---------------Timing errors: 0  Score: 0Constraints cover 63 paths, 0 nets, and 53 connections (100.0% coverage)Design statistics:   Minimum period:   9.938ns (Maximum frequency: 100.624MHz)   Maximum combinational path delay:  14.885ns   Minimum input arrival time before clock:   5.656ns   Maximum output required time before clock:  18.840nsAnalysis completed Tue Jan  6 18:04:14 1998--------------------------------------------------------------------------------

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