time_sim.v

实用的程序代码

// Xilinx Verilog produced by program ngd2ver, Version M1.4.12
// Date: Tue Jan  6 18:07:03 1998
// Design file: time_sim.nga
// Device: 4005epc84-2
`timescale 1 ns/1 ps
`uselib dir=/home/zeppelin2/tech_apps/m1_4.12/verilog/data libext=.vmd

  module binary (CLOCK, RESET, A, B, C, D, E, SINGLE, MULTI, CONTIG);
    input CLOCK;
    input RESET;
    input A;
    input B;
    input C;
    input D;
    input E;
    output SINGLE;
    output MULTI;
    output CONTIG;

    wire n128, n129, n130, n131, n132, n133, n134, n233, n234, n235, n195, n197
    , n196, n200, n198, n199, n201, n173, n202, n178, n179, n203, n204, n205, 
    n169, n207, n206, n177, n208, n209, n210, n211, n213, n171, n212, n175, n174
    , n214, n215, n168, n172, n216, n217, n218, n219, n220, n221, n222, n223, 
    n224, n225, n170, n228, n227, n226, n229, n230, n231, n232, 
    \U101/$1I20_GTS_TRI , \U102/$1I20_GTS_TRI , \U103/$1I20_GTS_TRI , 
    \CS_reg[0]/$1I13_GSR_OR , \CS_reg[1]/$1I13_GSR_OR , \CS_reg[2]/$1I13_GSR_OR 
    , \U94/clkio_bufsig , \U108/2_0 , \U113/2_0 , \U116/2_0 , \U126/2_0 , 
    \U135/2_0 , \U135/2_1 , \U137/2_0 , \U144/2_0 , \U147/2_0 , \U151/2_0 , 
    \U151/2_1 , \U153/2_0 , \U155/2_0 , U106_2_INV, U107_2_INV, U109_2_INV, 
    U111_2_INV, U112_2_INV, U120_2_INV, U127_2_INV, U128_2_INV, U136_2_INV, 
    U139_2_INV, U143_2_INV, U148_2_INV, \U135/n175_2_INV , \U151/n169_2_INV , 
    \U101/$1I20_GTS_TRI_2_INV , \U102/$1I20_GTS_TRI_2_INV , 
    \U103/$1I20_GTS_TRI_2_INV , GND, VCC;
    wire [2:0] CS;
    `ifdef GSR_SIGNAL
      wire GSR = `GSR_SIGNAL ;
    `else
      wire GSR ;
    `endif
    `ifdef GTS_SIGNAL
      wire GTS = `GTS_SIGNAL ;
    `else
      wire GTS ;
    `endif
    initial $sdf_annotate("time_sim.sdf");

    X_BUF U95 (.IN (RESET), .OUT (n129));
    X_BUF U96 (.IN (A), .OUT (n130));
    X_BUF U97 (.IN (B), .OUT (n131));
    X_BUF U98 (.IN (C), .OUT (n132));
    X_BUF U99 (.IN (D), .OUT (n133));
    X_BUF U100 (.IN (E), .OUT (n134));
    X_INV U104 (.IN (CS[2]), .OUT (n195));
    X_OR2 U105 (.IN0 (CS[0]), .IN1 (n195), .OUT (n197));
    X_AND2 U106 (.IN0 (CS[0]), .IN1 (CS[1]), .OUT (U106_2_INV));
    X_AND2 U107 (.IN0 (n196), .IN1 (n197), .OUT (U107_2_INV));
    X_AND2 U109 (.IN0 (n198), .IN1 (CS[2]), .OUT (U109_2_INV));
    X_INV U110 (.IN (CS[1]), .OUT (n198));
    X_AND2 U111 (.IN0 (n199), .IN1 (n200), .OUT (U111_2_INV));
    X_OR2 U112 (.IN0 (n173), .IN1 (n133), .OUT (U112_2_INV));
    X_INV U114 (.IN (n134), .OUT (n203));
    X_OR2 U115 (.IN0 (n203), .IN1 (CS[0]), .OUT (n204));
    X_INV U117 (.IN (n169), .OUT (n205));
    X_OR2 U118 (.IN0 (CS[0]), .IN1 (n205), .OUT (n207));
    X_OR2 U119 (.IN0 (n177), .IN1 (CS[1]), .OUT (n206));
    X_AND2 U120 (.IN0 (n206), .IN1 (n207), .OUT (U120_2_INV));
    X_XOR2 U121 (.IN0 (n132), .IN1 (n131), .OUT (n208));
    X_AND2 U122 (.IN0 (n208), .IN1 (n130), .OUT (n209));
    X_OR2 U123 (.IN0 (CS[2]), .IN1 (n209), .OUT (n177));
    X_INV U124 (.IN (CS[0]), .OUT (n210));
    X_INV U125 (.IN (CS[2]), .OUT (n211));
    X_AND2 U127 (.IN0 (n211), .IN1 (n175), .OUT (U127_2_INV));
    X_AND2 U128 (.IN0 (n212), .IN1 (n213), .OUT (U128_2_INV));
    X_OR2 U129 (.IN0 (n130), .IN1 (n133), .OUT (n214));
    X_AND2 U130 (.IN0 (n214), .IN1 (n168), .OUT (n215));
    X_OR2 U131 (.IN0 (n169), .IN1 (n215), .OUT (n172));
    X_AND2 U132 (.IN0 (n134), .IN1 (CS[1]), .OUT (n171));
    X_INV U133 (.IN (n132), .OUT (n216));
    X_INV U134 (.IN (n130), .OUT (n217));
    X_OR2 U136 (.IN0 (n173), .IN1 (n133), .OUT (U136_2_INV));
    X_INV U138 (.IN (n130), .OUT (n220));
    X_AND2 U139 (.IN0 (CS[1]), .IN1 (n220), .OUT (U139_2_INV));
    X_AND2 U140 (.IN0 (n221), .IN1 (CS[0]), .OUT (n222));
    X_OR2 U141 (.IN0 (CS[2]), .IN1 (n222), .OUT (n173));
    X_INV U142 (.IN (CS[2]), .OUT (n223));
    X_OR2 U143 (.IN0 (n171), .IN1 (n223), .OUT (U143_2_INV));
    X_INV U145 (.IN (n227), .OUT (n228));
    X_INV U146 (.IN (CS[1]), .OUT (n226));
    X_OR2 U148 (.IN0 (n228), .IN1 (CS[0]), .OUT (U148_2_INV));
    X_INV U149 (.IN (n131), .OUT (n229));
    X_INV U150 (.IN (n130), .OUT (n230));
    X_INV U152 (.IN (CS[2]), .OUT (n231));
    X_INV U154 (.IN (CS[0]), .OUT (n232));
    X_IPAD CLOCK_PAD (.PAD (CLOCK));
    X_IPAD RESET_PAD (.PAD (RESET));
    X_IPAD A_PAD (.PAD (A));
    X_IPAD B_PAD (.PAD (B));
    X_IPAD C_PAD (.PAD (C));
    X_IPAD D_PAD (.PAD (D));
    X_IPAD E_PAD (.PAD (E));
    X_OPAD SINGLE_PAD (.PAD (SINGLE));
    X_OPAD MULTI_PAD (.PAD (MULTI));
    X_OPAD CONTIG_PAD (.PAD (CONTIG));
    X_BUF \U101/$1I20  (.IN (n233), .OUT (\U101/$1I20_GTS_TRI ));
    X_TRI \U101/$1I20_GTS_TRI_128  (.IN (\U101/$1I20_GTS_TRI ), .OUT (SINGLE), 
    .CTL (\U101/$1I20_GTS_TRI_2_INV ));
    X_BUF \U102/$1I20  (.IN (n234), .OUT (\U102/$1I20_GTS_TRI ));
    X_TRI \U102/$1I20_GTS_TRI_129  (.IN (\U102/$1I20_GTS_TRI ), .OUT (MULTI), 
    .CTL (\U102/$1I20_GTS_TRI_2_INV ));
    X_BUF \U103/$1I20  (.IN (n235), .OUT (\U103/$1I20_GTS_TRI ));
    X_TRI \U103/$1I20_GTS_TRI_130  (.IN (\U103/$1I20_GTS_TRI ), .OUT (CONTIG), 
    .CTL (\U103/$1I20_GTS_TRI_2_INV ));
    X_FF \CS_reg<0>/$1I13  (.IN (n202), .CLK (n128), .CE (VCC), .SET 
    (\CS_reg[0]/$1I13_GSR_OR ), .RST (GND), .OUT (CS[0]));
    X_OR2 \CS_reg<0>/$1I13_GSR_OR_125  (.IN0 (n129), .IN1 (GSR), .OUT 
    (\CS_reg[0]/$1I13_GSR_OR ));
    X_FF \CS_reg<1>/$1I13  (.IN (n219), .CLK (n128), .CE (VCC), .SET (GND), 
    .RST (\CS_reg[1]/$1I13_GSR_OR ), .OUT (CS[1]));
    X_OR2 \CS_reg<1>/$1I13_GSR_OR_126  (.IN0 (n129), .IN1 (GSR), .OUT 
    (\CS_reg[1]/$1I13_GSR_OR ));
    X_FF \CS_reg<2>/$1I13  (.IN (n225), .CLK (n128), .CE (VCC), .SET (GND), 
    .RST (\CS_reg[2]/$1I13_GSR_OR ), .OUT (CS[2]));
    X_OR2 \CS_reg<2>/$1I13_GSR_OR_127  (.IN0 (n129), .IN1 (GSR), .OUT 
    (\CS_reg[2]/$1I13_GSR_OR ));
    X_CKBUF \U94/clkbuf  (.IN (\U94/clkio_bufsig ), .OUT (n128));
    X_BUF \U94/clkio_buf  (.IN (CLOCK), .OUT (\U94/clkio_bufsig ));
    X_OR2 \U108/n200/2_0  (.IN0 (CS[2]), .IN1 (CS[0]), .OUT (\U108/2_0 ));
    X_OR2 \U108/n200  (.IN0 (\U108/2_0 ), .IN1 (n198), .OUT (n200));
    X_OR2 \U113/n202/2_0  (.IN0 (n179), .IN1 (n201), .OUT (\U113/2_0 ));
    X_OR2 \U113/n202  (.IN0 (\U113/2_0 ), .IN1 (n178), .OUT (n202));
    X_AND2 \U116/n179/2_0  (.IN0 (CS[1]), .IN1 (n204), .OUT (\U116/2_0 ));
    X_AND2 \U116/n179  (.IN0 (\U116/2_0 ), .IN1 (CS[2]), .OUT (n179));
    X_OR2 \U126/n213/2_0  (.IN0 (n210), .IN1 (n171), .OUT (\U126/2_0 ));
    X_OR2 \U126/n213  (.IN0 (\U126/2_0 ), .IN1 (n211), .OUT (n213));
    X_OR2 \U135/n175/2_0  (.IN0 (n217), .IN1 (n216), .OUT (\U135/2_0 ));
    X_OR2 \U135/n175/2_1  (.IN0 (CS[1]), .IN1 (n131), .OUT (\U135/2_1 ));
    X_OR2 \U135/n175  (.IN0 (\U135/2_0 ), .IN1 (\U135/2_1 ), .OUT 
    (\U135/n175_2_INV ));
    X_OR2 \U137/n219/2_0  (.IN0 (n174), .IN1 (n218), .OUT (\U137/2_0 ));
    X_OR2 \U137/n219  (.IN0 (\U137/2_0 ), .IN1 (n233), .OUT (n219));
    X_OR2 \U144/n225/2_0  (.IN0 (n172), .IN1 (n224), .OUT (\U144/2_0 ));
    X_OR2 \U144/n225  (.IN0 (\U144/2_0 ), .IN1 (n170), .OUT (n225));
    X_OR2 \U147/n227/2_0  (.IN0 (n133), .IN1 (CS[2]), .OUT (\U147/2_0 ));
    X_OR2 \U147/n227  (.IN0 (\U147/2_0 ), .IN1 (n226), .OUT (n227));
    X_OR2 \U151/n169/2_0  (.IN0 (n230), .IN1 (n229), .OUT (\U151/2_0 ));
    X_OR2 \U151/n169/2_1  (.IN0 (CS[1]), .IN1 (n132), .OUT (\U151/2_1 ));
    X_OR2 \U151/n169  (.IN0 (\U151/2_0 ), .IN1 (\U151/2_1 ), .OUT 
    (\U151/n169_2_INV ));
    X_AND2 \U153/n168/2_0  (.IN0 (CS[0]), .IN1 (n231), .OUT (\U153/2_0 ));
    X_AND2 \U153/n168  (.IN0 (\U153/2_0 ), .IN1 (CS[1]), .OUT (n168));
    X_AND2 \U155/n233/2_0  (.IN0 (CS[1]), .IN1 (n232), .OUT (\U155/2_0 ));
    X_AND2 \U155/n233  (.IN0 (\U155/2_0 ), .IN1 (CS[2]), .OUT (n233));
    X_INV U106_2_INV_131 (.IN (U106_2_INV), .OUT (n196));
    X_INV U107_2_INV_132 (.IN (U107_2_INV), .OUT (n235));
    X_INV U109_2_INV_133 (.IN (U109_2_INV), .OUT (n199));
    X_INV U111_2_INV_134 (.IN (U111_2_INV), .OUT (n234));
    X_INV U112_2_INV_135 (.IN (U112_2_INV), .OUT (n201));
    X_INV U120_2_INV_136 (.IN (U120_2_INV), .OUT (n178));
    X_INV U127_2_INV_137 (.IN (U127_2_INV), .OUT (n212));
    X_INV U128_2_INV_138 (.IN (U128_2_INV), .OUT (n174));
    X_INV U136_2_INV_139 (.IN (U136_2_INV), .OUT (n218));
    X_INV U139_2_INV_140 (.IN (U139_2_INV), .OUT (n221));
    X_INV U143_2_INV_141 (.IN (U143_2_INV), .OUT (n224));
    X_INV U148_2_INV_142 (.IN (U148_2_INV), .OUT (n170));
    X_INV \U135/n175_2_INV_143  (.IN (\U135/n175_2_INV ), .OUT (n175));
    X_INV \U151/n169_2_INV_144  (.IN (\U151/n169_2_INV ), .OUT (n169));
    X_INV \U101/$1I20_GTS_TRI_2_INV_145  (.IN (GTS), .OUT 
    (\U101/$1I20_GTS_TRI_2_INV ));
    X_INV \U102/$1I20_GTS_TRI_2_INV_146  (.IN (GTS), .OUT 
    (\U102/$1I20_GTS_TRI_2_INV ));
    X_INV \U103/$1I20_GTS_TRI_2_INV_147  (.IN (GTS), .OUT 
    (\U103/$1I20_GTS_TRI_2_INV ));
    X_ONE VCC_148 (.OUT (VCC));
    X_ZERO GND_149 (.OUT (GND));
    X_PD NGD2VER_PD_110 (.OUT (GSR) );
    X_PD NGD2VER_PD_112 (.OUT (GTS) );
  endmodule