time_sim.vhd

实用的程序代码

    U770_N283 : X_OR2 
      port map ( I0 => U770_2_0 , I1 => U770_2_1 , O => U770_N283_2_INV ) ;
    U772_N282_2_0 : X_OR2 
      port map ( I0 => N81 , I1 => N82 , O => U772_2_0 ) ;
    U772_N282_2_1 : X_OR2 
      port map ( I0 => N83 , I1 => N740 , O => U772_2_1 ) ;
    U772_N282 : X_OR2 
      port map ( I0 => U772_2_0 , I1 => U772_2_1 , O => U772_N282_2_INV ) ;
    U774_N281_2_0 : X_OR2 
      port map ( I0 => N81 , I1 => N82 , O => U774_2_0 ) ;
    U774_N281_2_1 : X_OR2 
      port map ( I0 => N84 , I1 => N741 , O => U774_2_1 ) ;
    U774_N281 : X_OR2 
      port map ( I0 => U774_2_0 , I1 => U774_2_1 , O => U774_N281_2_INV ) ;
    U777_N280_2_0 : X_OR2 
      port map ( I0 => N743 , I1 => N742 , O => U777_2_0 ) ;
    U777_N280_2_1 : X_OR2 
      port map ( I0 => N82 , I1 => N81 , O => U777_2_1 ) ;
    U777_N280 : X_OR2 
      port map ( I0 => U777_2_0 , I1 => U777_2_1 , O => U777_N280_2_INV ) ;
    U779_N279_2_0 : X_OR2 
      port map ( I0 => N81 , I1 => N83 , O => U779_2_0 ) ;
    U779_N279_2_1 : X_OR2 
      port map ( I0 => N84 , I1 => N744 , O => U779_2_1 ) ;
    U779_N279 : X_OR2 
      port map ( I0 => U779_2_0 , I1 => U779_2_1 , O => U779_N279_2_INV ) ;
    U782_N278_2_0 : X_OR2 
      port map ( I0 => N746 , I1 => N745 , O => U782_2_0 ) ;
    U782_N278_2_1 : X_OR2 
      port map ( I0 => N83 , I1 => N81 , O => U782_2_1 ) ;
    U782_N278 : X_OR2 
      port map ( I0 => U782_2_0 , I1 => U782_2_1 , O => U782_N278_2_INV ) ;
    U785_N277_2_0 : X_OR2 
      port map ( I0 => N748 , I1 => N747 , O => U785_2_0 ) ;
    U785_N277_2_1 : X_OR2 
      port map ( I0 => N84 , I1 => N81 , O => U785_2_1 ) ;
    U785_N277 : X_OR2 
      port map ( I0 => U785_2_0 , I1 => U785_2_1 , O => U785_N277_2_INV ) ;
    U787_N750_2_0 : X_OR2 
      port map ( I0 => N417 , I1 => N418 , O => U787_2_0 ) ;
    U787_N750_2_1 : X_OR2 
      port map ( I0 => N419 , I1 => N420 , O => U787_2_1 ) ;
    U787_N750 : X_OR2 
      port map ( I0 => U787_2_0 , I1 => U787_2_1 , O => N750 ) ;
    U788_N749_2_0 : X_OR2 
      port map ( I0 => N413 , I1 => N414 , O => U788_2_0 ) ;
    U788_N749_2_1 : X_OR2 
      port map ( I0 => N415 , I1 => N416 , O => U788_2_1 ) ;
    U788_N749 : X_OR2 
      port map ( I0 => U788_2_0 , I1 => U788_2_1 , O => N749 ) ;
    U790_N752_2_0 : X_OR2 
      port map ( I0 => N409 , I1 => N410 , O => U790_2_0 ) ;
    U790_N752_2_1 : X_OR2 
      port map ( I0 => N411 , I1 => N412 , O => U790_2_1 ) ;
    U790_N752 : X_OR2 
      port map ( I0 => U790_2_0 , I1 => U790_2_1 , O => N752 ) ;
    U791_N751_2_0 : X_OR2 
      port map ( I0 => N405 , I1 => N406 , O => U791_2_0 ) ;
    U791_N751_2_1 : X_OR2 
      port map ( I0 => N407 , I1 => N408 , O => U791_2_1 ) ;
    U791_N751 : X_OR2 
      port map ( I0 => U791_2_0 , I1 => U791_2_1 , O => N751 ) ;
    U793_N754_2_0 : X_OR2 
      port map ( I0 => N401 , I1 => N402 , O => U793_2_0 ) ;
    U793_N754_2_1 : X_OR2 
      port map ( I0 => N403 , I1 => N404 , O => U793_2_1 ) ;
    U793_N754 : X_OR2 
      port map ( I0 => U793_2_0 , I1 => U793_2_1 , O => N754 ) ;
    U794_N753_2_0 : X_OR2 
      port map ( I0 => N397 , I1 => N398 , O => U794_2_0 ) ;
    U794_N753_2_1 : X_OR2 
      port map ( I0 => N399 , I1 => N400 , O => U794_2_1 ) ;
    U794_N753 : X_OR2 
      port map ( I0 => U794_2_0 , I1 => U794_2_1 , O => N753 ) ;
    U796_N756_2_0 : X_OR2 
      port map ( I0 => N393 , I1 => N394 , O => U796_2_0 ) ;
    U796_N756_2_1 : X_OR2 
      port map ( I0 => N395 , I1 => N396 , O => U796_2_1 ) ;
    U796_N756 : X_OR2 
      port map ( I0 => U796_2_0 , I1 => U796_2_1 , O => N756 ) ;
    U797_N755_2_0 : X_OR2 
      port map ( I0 => N389 , I1 => N390 , O => U797_2_0 ) ;
    U797_N755_2_1 : X_OR2 
      port map ( I0 => N391 , I1 => N392 , O => U797_2_1 ) ;
    U797_N755 : X_OR2 
      port map ( I0 => U797_2_0 , I1 => U797_2_1 , O => N755 ) ;
    U799_N758_2_0 : X_OR2 
      port map ( I0 => N385 , I1 => N386 , O => U799_2_0 ) ;
    U799_N758_2_1 : X_OR2 
      port map ( I0 => N387 , I1 => N388 , O => U799_2_1 ) ;
    U799_N758 : X_OR2 
      port map ( I0 => U799_2_0 , I1 => U799_2_1 , O => N758 ) ;
    U800_N757_2_0 : X_OR2 
      port map ( I0 => N381 , I1 => N382 , O => U800_2_0 ) ;
    U800_N757_2_1 : X_OR2 
      port map ( I0 => N383 , I1 => N384 , O => U800_2_1 ) ;
    U800_N757 : X_OR2 
      port map ( I0 => U800_2_0 , I1 => U800_2_1 , O => N757 ) ;
    U802_N760_2_0 : X_OR2 
      port map ( I0 => N373 , I1 => N374 , O => U802_2_0 ) ;
    U802_N760_2_1 : X_OR2 
      port map ( I0 => N375 , I1 => N376 , O => U802_2_1 ) ;
    U802_N760 : X_OR2 
      port map ( I0 => U802_2_0 , I1 => U802_2_1 , O => N760 ) ;
    U803_N759_2_0 : X_OR2 
      port map ( I0 => N377 , I1 => N378 , O => U803_2_0 ) ;
    U803_N759_2_1 : X_OR2 
      port map ( I0 => N379 , I1 => N380 , O => U803_2_1 ) ;
    U803_N759 : X_OR2 
      port map ( I0 => U803_2_0 , I1 => U803_2_1 , O => N759 ) ;
    U805_N762_2_0 : X_OR2 
      port map ( I0 => N369 , I1 => N370 , O => U805_2_0 ) ;
    U805_N762_2_1 : X_OR2 
      port map ( I0 => N371 , I1 => N372 , O => U805_2_1 ) ;
    U805_N762 : X_OR2 
      port map ( I0 => U805_2_0 , I1 => U805_2_1 , O => N762 ) ;
    U806_N761_2_0 : X_OR2 
      port map ( I0 => N365 , I1 => N366 , O => U806_2_0 ) ;
    U806_N761_2_1 : X_OR2 
      port map ( I0 => N367 , I1 => N368 , O => U806_2_1 ) ;
    U806_N761 : X_OR2 
      port map ( I0 => U806_2_0 , I1 => U806_2_1 , O => N761 ) ;
    U808_N764_2_0 : X_OR2 
      port map ( I0 => N361 , I1 => N362 , O => U808_2_0 ) ;
    U808_N764_2_1 : X_OR2 
      port map ( I0 => N363 , I1 => N364 , O => U808_2_1 ) ;
    U808_N764 : X_OR2 
      port map ( I0 => U808_2_0 , I1 => U808_2_1 , O => N764 ) ;
    U809_N763_2_0 : X_OR2 
      port map ( I0 => N357 , I1 => N358 , O => U809_2_0 ) ;
    U809_N763_2_1 : X_OR2 
      port map ( I0 => N359 , I1 => N360 , O => U809_2_1 ) ;
    U809_N763 : X_OR2 
      port map ( I0 => U809_2_0 , I1 => U809_2_1 , O => N763 ) ;
    U811_N766_2_0 : X_OR2 
      port map ( I0 => N353 , I1 => N354 , O => U811_2_0 ) ;
    U811_N766_2_1 : X_OR2 
      port map ( I0 => N355 , I1 => N356 , O => U811_2_1 ) ;
    U811_N766 : X_OR2 
      port map ( I0 => U811_2_0 , I1 => U811_2_1 , O => N766 ) ;
    U812_N765_2_0 : X_OR2 
      port map ( I0 => N349 , I1 => N350 , O => U812_2_0 ) ;
    U812_N765_2_1 : X_OR2 
      port map ( I0 => N351 , I1 => N352 , O => U812_2_1 ) ;
    U812_N765 : X_OR2 
      port map ( I0 => U812_2_0 , I1 => U812_2_1 , O => N765 ) ;
    U814_N768_2_0 : X_OR2 
      port map ( I0 => N345 , I1 => N346 , O => U814_2_0 ) ;
    U814_N768_2_1 : X_OR2 
      port map ( I0 => N347 , I1 => N348 , O => U814_2_1 ) ;
    U814_N768 : X_OR2 
      port map ( I0 => U814_2_0 , I1 => U814_2_1 , O => N768 ) ;
    U815_N767_2_0 : X_OR2 
      port map ( I0 => N341 , I1 => N342 , O => U815_2_0 ) ;
    U815_N767_2_1 : X_OR2 
      port map ( I0 => N343 , I1 => N344 , O => U815_2_1 ) ;
    U815_N767 : X_OR2 
      port map ( I0 => U815_2_0 , I1 => U815_2_1 , O => N767 ) ;
    U817_N770_2_0 : X_OR2 
      port map ( I0 => N337 , I1 => N338 , O => U817_2_0 ) ;
    U817_N770_2_1 : X_OR2 
      port map ( I0 => N339 , I1 => N340 , O => U817_2_1 ) ;
    U817_N770 : X_OR2 
      port map ( I0 => U817_2_0 , I1 => U817_2_1 , O => N770 ) ;
    U818_N769_2_0 : X_OR2 
      port map ( I0 => N333 , I1 => N334 , O => U818_2_0 ) ;
    U818_N769_2_1 : X_OR2 
      port map ( I0 => N335 , I1 => N336 , O => U818_2_1 ) ;
    U818_N769 : X_OR2 
      port map ( I0 => U818_2_0 , I1 => U818_2_1 , O => N769 ) ;
    U820_N772_2_0 : X_OR2 
      port map ( I0 => N329 , I1 => N330 , O => U820_2_0 ) ;
    U820_N772_2_1 : X_OR2 
      port map ( I0 => N331 , I1 => N332 , O => U820_2_1 ) ;
    U820_N772 : X_OR2 
      port map ( I0 => U820_2_0 , I1 => U820_2_1 , O => N772 ) ;
    U821_N771_2_0 : X_OR2 
      port map ( I0 => N325 , I1 => N326 , O => U821_2_0 ) ;
    U821_N771_2_1 : X_OR2 
      port map ( I0 => N327 , I1 => N328 , O => U821_2_1 ) ;
    U821_N771 : X_OR2 
      port map ( I0 => U821_2_0 , I1 => U821_2_1 , O => N771 ) ;
    U823_N774_2_0 : X_OR2 
      port map ( I0 => N317 , I1 => N318 , O => U823_2_0 ) ;
    U823_N774_2_1 : X_OR2 
      port map ( I0 => N319 , I1 => N320 , O => U823_2_1 ) ;
    U823_N774 : X_OR2 
      port map ( I0 => U823_2_0 , I1 => U823_2_1 , O => N774 ) ;
    U824_N773_2_0 : X_OR2 
      port map ( I0 => N321 , I1 => N322 , O => U824_2_0 ) ;
    U824_N773_2_1 : X_OR2 
      port map ( I0 => N323 , I1 => N324 , O => U824_2_1 ) ;
    U824_N773 : X_OR2 
      port map ( I0 => U824_2_0 , I1 => U824_2_1 , O => N773 ) ;
    U826_N776_2_0 : X_OR2 
      port map ( I0 => N309 , I1 => N310 , O => U826_2_0 ) ;
    U826_N776_2_1 : X_OR2 
      port map ( I0 => N311 , I1 => N312 , O => U826_2_1 ) ;
    U826_N776 : X_OR2 
      port map ( I0 => U826_2_0 , I1 => U826_2_1 , O => N776 ) ;
    U827_N775_2_0 : X_OR2 
      port map ( I0 => N313 , I1 => N314 , O => U827_2_0 ) ;
    U827_N775_2_1 : X_OR2 
      port map ( I0 => N315 , I1 => N316 , O => U827_2_1 ) ;
    U827_N775 : X_OR2 
      port map ( I0 => U827_2_0 , I1 => U827_2_1 , O => N775 ) ;
    U829_N778_2_0 : X_OR2 
      port map ( I0 => N305 , I1 => N306 , O => U829_2_0 ) ;
    U829_N778_2_1 : X_OR2 
      port map ( I0 => N307 , I1 => N308 , O => U829_2_1 ) ;
    U829_N778 : X_OR2 
      port map ( I0 => U829_2_0 , I1 => U829_2_1 , O => N778 ) ;
    U830_N777_2_0 : X_OR2 
      port map ( I0 => N301 , I1 => N302 , O => U830_2_0 ) ;
    U830_N777_2_1 : X_OR2 
      port map ( I0 => N303 , I1 => N304 , O => U830_2_1 ) ;
    U830_N777 : X_OR2 
      port map ( I0 => U830_2_0 , I1 => U830_2_1 , O => N777 ) ;
    U832_N780_2_0 : X_OR2 
      port map ( I0 => N297 , I1 => N298 , O => U832_2_0 ) ;
    U832_N780_2_1 : X_OR2 
      port map ( I0 => N299 , I1 => N300 , O => U832_2_1 ) ;
    U832_N780 : X_OR2 
      port map ( I0 => U832_2_0 , I1 => U832_2_1 , O => N780 ) ;
    U833_N779_2_0 : X_OR2 
      port map ( I0 => N293 , I1 => N294 , O => U833_2_0 ) ;
    U833_N779_2_1 : X_OR2 
      port map ( I0 => N295 , I1 => N296 , O => U833_2_1 ) ;
    U833_N779 : X_OR2 
      port map ( I0 => U833_2_0 , I1 => U833_2_1 , O => N779 ) ;
    U366_2_INV_16 : X_INV 
      port map ( I => U366_2_INV , O => N474 ) ;
    U367_2_INV_17 : X_INV 
      port map ( I => U367_2_INV , O => N473 ) ;
    U368_2_INV_18 : X_INV 
      port map ( I => U368_2_INV , O => N420 ) ;
    U369_2_INV_19 : X_INV 
      port map ( I => U369_2_INV , O => N476 ) ;
    U370_2_INV_20 : X_INV 
      port map ( I => U370_2_INV , O => N475 ) ;
    U371_2_INV_21 : X_INV 
      port map ( I => U371_2_INV , O => N419 ) ;
    U372_2_INV_22 : X_INV 
      port map ( I => U372_2_INV , O => N478 ) ;
    U373_2_INV_23 : X_INV 
      port map ( I => U373_2_INV , O => N477 ) ;
    U374_2_INV_24 : X_INV 
      port map ( I => U374_2_INV , O => N418 ) ;
    U375_2_INV_25 : X_INV 
      port map ( I => U375_2_INV , O => N480 ) ;
    U376_2_INV_26 : X_INV 
      port map ( I => U376_2_INV , O => N479 ) ;
    U377_2_INV_27 : X_INV 
      port map ( I => U377_2_INV , O => N417 ) ;
    U378_2_INV_28 : X_INV 
      port map ( I => U378_2_INV , O => N482 ) ;
    U379_2_INV_29 : X_INV 
      port map ( I => U379_2_INV , O => N481 ) ;
    U380_2_INV_30 : X_INV 
      port map ( I => U380_2_INV , O => N416 ) ;
    U381_2_INV_31 : X_INV 
      port map ( I => U381_2_INV , O => N484 ) ;
    U382_2_INV_32 : X_INV 
      port map ( I => U382_2_INV , O => N483 ) ;
    U383_2_INV_33 : X_INV 
      port map ( I => U383_2_INV , O => N415 ) ;
    U384_2_INV_34 : X_INV 
      port map ( I => U384_2_INV , O => N486 ) ;
    U385_2_INV_35 : X_INV 
      port map ( I => U385_2_INV , O => N485 ) ;
    U386_2_INV_36 : X_INV 
      port map ( I => U386_2_INV , O => N414 ) ;
    U387_2_INV_37 : X_INV 
      port map ( I => U387_2_INV , O => N488 ) ;
    U388_2_INV_38 : X_INV 
      port map ( I => U388_2_INV , O => N487 ) ;
    U389_2_INV_39 : X_INV 
      port map ( I => U389_2_INV , O => N413 ) ;
    U390_2_INV_40 : X_INV 
      port map ( I => U390_2_INV , O => N490 ) ;
    U391_2_INV_41 : X_INV 
      port map ( I => U391_2_INV , O => N489 ) ;
    U392_2_INV_42 : X_INV 
      port map ( I => U392_2_INV , O => N412 ) ;
    U393_2_INV_43 : X_INV 
      port map ( I => U393_2_INV , O => N492 ) ;
    U394_2_INV_44 : X_INV 
      port map ( I => U394_2_INV , O => N491 ) ;
    U395_2_INV_45 : X_INV 
      port map ( I => U395_2_INV , O => N411 ) ;
    U396_2_INV_46 : X_INV 
      port map ( I => U396_2_INV , O => N494 ) ;
    U397_2_INV_47 : X_INV 
      port map ( I => U397_2_INV , O => N493 ) ;
    U398_2_INV_48 : X_INV 
      port map ( I => U398_2_INV , O => N410 ) ;
    U399_2_INV_49 : X_INV 
      port map ( I => U399_2_INV , O =>