time_sim.vhd

实用的程序代码

    U705 : X_AND2 
      port map ( I0 => N278 , I1 => N87 , O => U705_2_INV ) ;
    U706 : X_AND2 
      port map ( I0 => N279 , I1 => N88 , O => U706_2_INV ) ;
    U707 : X_AND2 
      port map ( I0 => N699 , I1 => N700 , O => U707_2_INV ) ;
    U708 : X_AND2 
      port map ( I0 => N280 , I1 => N89 , O => U708_2_INV ) ;
    U709 : X_AND2 
      port map ( I0 => N281 , I1 => N90 , O => U709_2_INV ) ;
    U710 : X_AND2 
      port map ( I0 => N701 , I1 => N702 , O => U710_2_INV ) ;
    U711 : X_AND2 
      port map ( I0 => N282 , I1 => N91 , O => U711_2_INV ) ;
    U712 : X_AND2 
      port map ( I0 => N283 , I1 => N92 , O => U712_2_INV ) ;
    U713 : X_AND2 
      port map ( I0 => N703 , I1 => N704 , O => U713_2_INV ) ;
    U714 : X_AND2 
      port map ( I0 => N284 , I1 => N93 , O => U714_2_INV ) ;
    U715 : X_AND2 
      port map ( I0 => N285 , I1 => N94 , O => U715_2_INV ) ;
    U716 : X_AND2 
      port map ( I0 => N705 , I1 => N706 , O => U716_2_INV ) ;
    U717 : X_AND2 
      port map ( I0 => N286 , I1 => N95 , O => U717_2_INV ) ;
    U718 : X_AND2 
      port map ( I0 => N287 , I1 => N96 , O => U718_2_INV ) ;
    U719 : X_AND2 
      port map ( I0 => N707 , I1 => N708 , O => U719_2_INV ) ;
    U720 : X_AND2 
      port map ( I0 => N288 , I1 => N97 , O => U720_2_INV ) ;
    U721 : X_AND2 
      port map ( I0 => N289 , I1 => N98 , O => U721_2_INV ) ;
    U722 : X_AND2 
      port map ( I0 => N709 , I1 => N710 , O => U722_2_INV ) ;
    U723 : X_AND2 
      port map ( I0 => N290 , I1 => N99 , O => U723_2_INV ) ;
    U724 : X_AND2 
      port map ( I0 => N291 , I1 => N100 , O => U724_2_INV ) ;
    U725 : X_AND2 
      port map ( I0 => N711 , I1 => N712 , O => U725_2_INV ) ;
    U726 : X_AND2 
      port map ( I0 => N277 , I1 => N85 , O => U726_2_INV ) ;
    U727 : X_AND2 
      port map ( I0 => N278 , I1 => N86 , O => U727_2_INV ) ;
    U728 : X_AND2 
      port map ( I0 => N713 , I1 => N714 , O => U728_2_INV ) ;
    U729 : X_AND2 
      port map ( I0 => N279 , I1 => N87 , O => U729_2_INV ) ;
    U730 : X_AND2 
      port map ( I0 => N280 , I1 => N88 , O => U730_2_INV ) ;
    U731 : X_AND2 
      port map ( I0 => N715 , I1 => N716 , O => U731_2_INV ) ;
    U732 : X_AND2 
      port map ( I0 => N281 , I1 => N89 , O => U732_2_INV ) ;
    U733 : X_AND2 
      port map ( I0 => N282 , I1 => N90 , O => U733_2_INV ) ;
    U734 : X_AND2 
      port map ( I0 => N717 , I1 => N718 , O => U734_2_INV ) ;
    U735 : X_AND2 
      port map ( I0 => N283 , I1 => N91 , O => U735_2_INV ) ;
    U736 : X_AND2 
      port map ( I0 => N284 , I1 => N92 , O => U736_2_INV ) ;
    U737 : X_AND2 
      port map ( I0 => N719 , I1 => N720 , O => U737_2_INV ) ;
    U738 : X_AND2 
      port map ( I0 => N285 , I1 => N93 , O => U738_2_INV ) ;
    U739 : X_AND2 
      port map ( I0 => N286 , I1 => N94 , O => U739_2_INV ) ;
    U740 : X_AND2 
      port map ( I0 => N721 , I1 => N722 , O => U740_2_INV ) ;
    U741 : X_AND2 
      port map ( I0 => N287 , I1 => N95 , O => U741_2_INV ) ;
    U742 : X_AND2 
      port map ( I0 => N288 , I1 => N96 , O => U742_2_INV ) ;
    U743 : X_AND2 
      port map ( I0 => N723 , I1 => N724 , O => U743_2_INV ) ;
    U744 : X_AND2 
      port map ( I0 => N289 , I1 => N97 , O => U744_2_INV ) ;
    U745 : X_AND2 
      port map ( I0 => N290 , I1 => N98 , O => U745_2_INV ) ;
    U746 : X_AND2 
      port map ( I0 => N725 , I1 => N726 , O => U746_2_INV ) ;
    U747 : X_AND2 
      port map ( I0 => N291 , I1 => N99 , O => U747_2_INV ) ;
    U748 : X_AND2 
      port map ( I0 => N292 , I1 => N100 , O => U748_2_INV ) ;
    U749 : X_AND2 
      port map ( I0 => N727 , I1 => N728 , O => U749_2_INV ) ;
    U750 : X_INV 
      port map ( I => N81 , O => N729 ) ;
    U752 : X_INV 
      port map ( I => N81 , O => N730 ) ;
    U754 : X_INV 
      port map ( I => N84 , O => N731 ) ;
    U755 : X_INV 
      port map ( I => N81 , O => N732 ) ;
    U757 : X_INV 
      port map ( I => N83 , O => N733 ) ;
    U758 : X_INV 
      port map ( I => N81 , O => N734 ) ;
    U760 : X_INV 
      port map ( I => N82 , O => N735 ) ;
    U762 : X_INV 
      port map ( I => N82 , O => N736 ) ;
    U763 : X_INV 
      port map ( I => N81 , O => N737 ) ;
    U765 : X_INV 
      port map ( I => N83 , O => N738 ) ;
    U767 : X_INV 
      port map ( I => N84 , O => N739 ) ;
    U771 : X_INV 
      port map ( I => N84 , O => N740 ) ;
    U773 : X_INV 
      port map ( I => N83 , O => N741 ) ;
    U775 : X_INV 
      port map ( I => N84 , O => N742 ) ;
    U776 : X_INV 
      port map ( I => N83 , O => N743 ) ;
    U778 : X_INV 
      port map ( I => N82 , O => N744 ) ;
    U780 : X_INV 
      port map ( I => N84 , O => N745 ) ;
    U781 : X_INV 
      port map ( I => N82 , O => N746 ) ;
    U783 : X_INV 
      port map ( I => N83 , O => N747 ) ;
    U784 : X_INV 
      port map ( I => N82 , O => N748 ) ;
    U786 : X_OR2 
      port map ( I0 => N749 , I1 => N750 , O => N796 ) ;
    U789 : X_OR2 
      port map ( I0 => N751 , I1 => N752 , O => N786 ) ;
    U792 : X_OR2 
      port map ( I0 => N753 , I1 => N754 , O => N785 ) ;
    U795 : X_OR2 
      port map ( I0 => N755 , I1 => N756 , O => N784 ) ;
    U798 : X_OR2 
      port map ( I0 => N757 , I1 => N758 , O => N783 ) ;
    U801 : X_OR2 
      port map ( I0 => N760 , I1 => N759 , O => N782 ) ;
    U804 : X_OR2 
      port map ( I0 => N761 , I1 => N762 , O => N781 ) ;
    U807 : X_OR2 
      port map ( I0 => N763 , I1 => N764 , O => N795 ) ;
    U810 : X_OR2 
      port map ( I0 => N765 , I1 => N766 , O => N794 ) ;
    U813 : X_OR2 
      port map ( I0 => N767 , I1 => N768 , O => N793 ) ;
    U816 : X_OR2 
      port map ( I0 => N769 , I1 => N770 , O => N792 ) ;
    U819 : X_OR2 
      port map ( I0 => N771 , I1 => N772 , O => N791 ) ;
    U822 : X_OR2 
      port map ( I0 => N774 , I1 => N773 , O => N790 ) ;
    U825 : X_OR2 
      port map ( I0 => N776 , I1 => N775 , O => N789 ) ;
    U828 : X_OR2 
      port map ( I0 => N777 , I1 => N778 , O => N788 ) ;
    U831 : X_OR2 
      port map ( I0 => N779 , I1 => N780 , O => N787 ) ;
    U350_1I20 : X_BUF 
      port map ( I => N781 , O => U350_1I20_GTS_TRI ) ;
    U350_1I20_GTS_TRI_0 : X_TRI 
      port map ( I => U350_1I20_GTS_TRI , O => B_P(15) , 
      CTL => U350_1I20_GTS_TRI_2_INV ) ;
    U351_1I20 : X_BUF 
      port map ( I => N782 , O => U351_1I20_GTS_TRI ) ;
    U351_1I20_GTS_TRI_1 : X_TRI 
      port map ( I => U351_1I20_GTS_TRI , O => B_P(14) , 
      CTL => U351_1I20_GTS_TRI_2_INV ) ;
    U352_1I20 : X_BUF 
      port map ( I => N783 , O => U352_1I20_GTS_TRI ) ;
    U352_1I20_GTS_TRI_2 : X_TRI 
      port map ( I => U352_1I20_GTS_TRI , O => B_P(13) , 
      CTL => U352_1I20_GTS_TRI_2_INV ) ;
    U353_1I20 : X_BUF 
      port map ( I => N784 , O => U353_1I20_GTS_TRI ) ;
    U353_1I20_GTS_TRI_3 : X_TRI 
      port map ( I => U353_1I20_GTS_TRI , O => B_P(12) , 
      CTL => U353_1I20_GTS_TRI_2_INV ) ;
    U354_1I20 : X_BUF 
      port map ( I => N785 , O => U354_1I20_GTS_TRI ) ;
    U354_1I20_GTS_TRI_4 : X_TRI 
      port map ( I => U354_1I20_GTS_TRI , O => B_P(11) , 
      CTL => U354_1I20_GTS_TRI_2_INV ) ;
    U355_1I20 : X_BUF 
      port map ( I => N786 , O => U355_1I20_GTS_TRI ) ;
    U355_1I20_GTS_TRI_5 : X_TRI 
      port map ( I => U355_1I20_GTS_TRI , O => B_P(10) , 
      CTL => U355_1I20_GTS_TRI_2_INV ) ;
    U356_1I20 : X_BUF 
      port map ( I => N787 , O => U356_1I20_GTS_TRI ) ;
    U356_1I20_GTS_TRI_6 : X_TRI 
      port map ( I => U356_1I20_GTS_TRI , O => B_P(9) , 
      CTL => U356_1I20_GTS_TRI_2_INV ) ;
    U357_1I20 : X_BUF 
      port map ( I => N788 , O => U357_1I20_GTS_TRI ) ;
    U357_1I20_GTS_TRI_7 : X_TRI 
      port map ( I => U357_1I20_GTS_TRI , O => B_P(8) , 
      CTL => U357_1I20_GTS_TRI_2_INV ) ;
    U358_1I20 : X_BUF 
      port map ( I => N789 , O => U358_1I20_GTS_TRI ) ;
    U358_1I20_GTS_TRI_8 : X_TRI 
      port map ( I => U358_1I20_GTS_TRI , O => B_P(7) , 
      CTL => U358_1I20_GTS_TRI_2_INV ) ;
    U359_1I20 : X_BUF 
      port map ( I => N790 , O => U359_1I20_GTS_TRI ) ;
    U359_1I20_GTS_TRI_9 : X_TRI 
      port map ( I => U359_1I20_GTS_TRI , O => B_P(6) , 
      CTL => U359_1I20_GTS_TRI_2_INV ) ;
    U360_1I20 : X_BUF 
      port map ( I => N791 , O => U360_1I20_GTS_TRI ) ;
    U360_1I20_GTS_TRI_10 : X_TRI 
      port map ( I => U360_1I20_GTS_TRI , O => B_P(5) , 
      CTL => U360_1I20_GTS_TRI_2_INV ) ;
    U361_1I20 : X_BUF 
      port map ( I => N792 , O => U361_1I20_GTS_TRI ) ;
    U361_1I20_GTS_TRI_11 : X_TRI 
      port map ( I => U361_1I20_GTS_TRI , O => B_P(4) , 
      CTL => U361_1I20_GTS_TRI_2_INV ) ;
    U362_1I20 : X_BUF 
      port map ( I => N793 , O => U362_1I20_GTS_TRI ) ;
    U362_1I20_GTS_TRI_12 : X_TRI 
      port map ( I => U362_1I20_GTS_TRI , O => B_P(3) , 
      CTL => U362_1I20_GTS_TRI_2_INV ) ;
    U363_1I20 : X_BUF 
      port map ( I => N794 , O => U363_1I20_GTS_TRI ) ;
    U363_1I20_GTS_TRI_13 : X_TRI 
      port map ( I => U363_1I20_GTS_TRI , O => B_P(2) , 
      CTL => U363_1I20_GTS_TRI_2_INV ) ;
    U364_1I20 : X_BUF 
      port map ( I => N795 , O => U364_1I20_GTS_TRI ) ;
    U364_1I20_GTS_TRI_14 : X_TRI 
      port map ( I => U364_1I20_GTS_TRI , O => B_P(1) , 
      CTL => U364_1I20_GTS_TRI_2_INV ) ;
    U365_1I20 : X_BUF 
      port map ( I => N796 , O => U365_1I20_GTS_TRI ) ;
    U365_1I20_GTS_TRI_15 : X_TRI 
      port map ( I => U365_1I20_GTS_TRI , O => B_P(0) , 
      CTL => U365_1I20_GTS_TRI_2_INV ) ;
    U751_N292_2_0 : X_AND2 
      port map ( I0 => N82 , I1 => N83 , O => U751_2_0 ) ;
    U751_N292_2_1 : X_AND2 
      port map ( I0 => N84 , I1 => N729 , O => U751_2_1 ) ;
    U751_N292 : X_AND2 
      port map ( I0 => U751_2_0 , I1 => U751_2_1 , O => N292 ) ;
    U753_N291_2_0 : X_OR2 
      port map ( I0 => N82 , I1 => N83 , O => U753_2_0 ) ;
    U753_N291_2_1 : X_OR2 
      port map ( I0 => N84 , I1 => N730 , O => U753_2_1 ) ;
    U753_N291 : X_OR2 
      port map ( I0 => U753_2_0 , I1 => U753_2_1 , O => U753_N291_2_INV ) ;
    U756_N290_2_0 : X_OR2 
      port map ( I0 => N732 , I1 => N731 , O => U756_2_0 ) ;
    U756_N290_2_1 : X_OR2 
      port map ( I0 => N83 , I1 => N82 , O => U756_2_1 ) ;
    U756_N290 : X_OR2 
      port map ( I0 => U756_2_0 , I1 => U756_2_1 , O => U756_N290_2_INV ) ;
    U759_N289_2_0 : X_OR2 
      port map ( I0 => N734 , I1 => N733 , O => U759_2_0 ) ;
    U759_N289_2_1 : X_OR2 
      port map ( I0 => N84 , I1 => N82 , O => U759_2_1 ) ;
    U759_N289 : X_OR2 
      port map ( I0 => U759_2_0 , I1 => U759_2_1 , O => U759_N289_2_INV ) ;
    U761_N288_2_0 : X_AND2 
      port map ( I0 => N81 , I1 => N83 , O => U761_2_0 ) ;
    U761_N288_2_1 : X_AND2 
      port map ( I0 => N84 , I1 => N735 , O => U761_2_1 ) ;
    U761_N288 : X_AND2 
      port map ( I0 => U761_2_0 , I1 => U761_2_1 , O => N288 ) ;
    U764_N287_2_0 : X_OR2 
      port map ( I0 => N737 , I1 => N736 , O => U764_2_0 ) ;
    U764_N287_2_1 : X_OR2 
      port map ( I0 => N84 , I1 => N83 , O => U764_2_1 ) ;
    U764_N287 : X_OR2 
      port map ( I0 => U764_2_0 , I1 => U764_2_1 , O => U764_N287_2_INV ) ;
    U766_N286_2_0 : X_AND2 
      port map ( I0 => N81 , I1 => N82 , O => U766_2_0 ) ;
    U766_N286_2_1 : X_AND2 
      port map ( I0 => N84 , I1 => N738 , O => U766_2_1 ) ;
    U766_N286 : X_AND2 
      port map ( I0 => U766_2_0 , I1 => U766_2_1 , O => N286 ) ;
    U768_N285_2_0 : X_AND2 
      port map ( I0 => N81 , I1 => N82 , O => U768_2_0 ) ;
    U768_N285_2_1 : X_AND2 
      port map ( I0 => N83 , I1 => N739 , O => U768_2_1 ) ;
    U768_N285 : X_AND2 
      port map ( I0 => U768_2_0 , I1 => U768_2_1 , O => N285 ) ;
    U769_N284_2_0 : X_AND2 
      port map ( I0 => N81 , I1 => N82 , O => U769_2_0 ) ;
    U769_N284_2_1 : X_AND2 
      port map ( I0 => N83 , I1 => N84 , O => U769_2_1 ) ;
    U769_N284 : X_AND2 
      port map ( I0 => U769_2_0 , I1 => U769_2_1 , O => N284 ) ;
    U770_N283_2_0 : X_OR2 
      port map ( I0 => N81 , I1 => N82 , O => U770_2_0 ) ;
    U770_N283_2_1 : X_OR2 
      port map ( I0 => N83 , I1 => N84 , O => U770_2_1 ) ;