time_sim.vhd

实用的程序代码

    U555 : X_AND2 
      port map ( I0 => N283 , I1 => N99 , O => U555_2_INV ) ;
    U556 : X_AND2 
      port map ( I0 => N284 , I1 => N100 , O => U556_2_INV ) ;
    U557 : X_AND2 
      port map ( I0 => N599 , I1 => N600 , O => U557_2_INV ) ;
    U558 : X_AND2 
      port map ( I0 => N286 , I1 => N85 , O => U558_2_INV ) ;
    U559 : X_AND2 
      port map ( I0 => N287 , I1 => N86 , O => U559_2_INV ) ;
    U560 : X_AND2 
      port map ( I0 => N601 , I1 => N602 , O => U560_2_INV ) ;
    U561 : X_AND2 
      port map ( I0 => N288 , I1 => N87 , O => U561_2_INV ) ;
    U562 : X_AND2 
      port map ( I0 => N289 , I1 => N88 , O => U562_2_INV ) ;
    U563 : X_AND2 
      port map ( I0 => N603 , I1 => N604 , O => U563_2_INV ) ;
    U564 : X_AND2 
      port map ( I0 => N290 , I1 => N89 , O => U564_2_INV ) ;
    U565 : X_AND2 
      port map ( I0 => N291 , I1 => N90 , O => U565_2_INV ) ;
    U566 : X_AND2 
      port map ( I0 => N605 , I1 => N606 , O => U566_2_INV ) ;
    U567 : X_AND2 
      port map ( I0 => N277 , I1 => N92 , O => U567_2_INV ) ;
    U568 : X_AND2 
      port map ( I0 => N292 , I1 => N91 , O => U568_2_INV ) ;
    U569 : X_AND2 
      port map ( I0 => N607 , I1 => N608 , O => U569_2_INV ) ;
    U570 : X_AND2 
      port map ( I0 => N278 , I1 => N93 , O => U570_2_INV ) ;
    U571 : X_AND2 
      port map ( I0 => N279 , I1 => N94 , O => U571_2_INV ) ;
    U572 : X_AND2 
      port map ( I0 => N609 , I1 => N610 , O => U572_2_INV ) ;
    U573 : X_AND2 
      port map ( I0 => N280 , I1 => N95 , O => U573_2_INV ) ;
    U574 : X_AND2 
      port map ( I0 => N281 , I1 => N96 , O => U574_2_INV ) ;
    U575 : X_AND2 
      port map ( I0 => N611 , I1 => N612 , O => U575_2_INV ) ;
    U576 : X_AND2 
      port map ( I0 => N282 , I1 => N97 , O => U576_2_INV ) ;
    U577 : X_AND2 
      port map ( I0 => N283 , I1 => N98 , O => U577_2_INV ) ;
    U578 : X_AND2 
      port map ( I0 => N613 , I1 => N614 , O => U578_2_INV ) ;
    U579 : X_AND2 
      port map ( I0 => N284 , I1 => N99 , O => U579_2_INV ) ;
    U580 : X_AND2 
      port map ( I0 => N285 , I1 => N100 , O => U580_2_INV ) ;
    U581 : X_AND2 
      port map ( I0 => N615 , I1 => N616 , O => U581_2_INV ) ;
    U582 : X_AND2 
      port map ( I0 => N287 , I1 => N85 , O => U582_2_INV ) ;
    U583 : X_AND2 
      port map ( I0 => N288 , I1 => N86 , O => U583_2_INV ) ;
    U584 : X_AND2 
      port map ( I0 => N617 , I1 => N618 , O => U584_2_INV ) ;
    U585 : X_AND2 
      port map ( I0 => N289 , I1 => N87 , O => U585_2_INV ) ;
    U586 : X_AND2 
      port map ( I0 => N290 , I1 => N88 , O => U586_2_INV ) ;
    U587 : X_AND2 
      port map ( I0 => N619 , I1 => N620 , O => U587_2_INV ) ;
    U588 : X_AND2 
      port map ( I0 => N291 , I1 => N89 , O => U588_2_INV ) ;
    U589 : X_AND2 
      port map ( I0 => N292 , I1 => N90 , O => U589_2_INV ) ;
    U590 : X_AND2 
      port map ( I0 => N621 , I1 => N622 , O => U590_2_INV ) ;
    U591 : X_AND2 
      port map ( I0 => N277 , I1 => N91 , O => U591_2_INV ) ;
    U592 : X_AND2 
      port map ( I0 => N278 , I1 => N92 , O => U592_2_INV ) ;
    U593 : X_AND2 
      port map ( I0 => N623 , I1 => N624 , O => U593_2_INV ) ;
    U594 : X_AND2 
      port map ( I0 => N279 , I1 => N93 , O => U594_2_INV ) ;
    U595 : X_AND2 
      port map ( I0 => N280 , I1 => N94 , O => U595_2_INV ) ;
    U596 : X_AND2 
      port map ( I0 => N625 , I1 => N626 , O => U596_2_INV ) ;
    U597 : X_AND2 
      port map ( I0 => N281 , I1 => N95 , O => U597_2_INV ) ;
    U598 : X_AND2 
      port map ( I0 => N282 , I1 => N96 , O => U598_2_INV ) ;
    U599 : X_AND2 
      port map ( I0 => N627 , I1 => N628 , O => U599_2_INV ) ;
    U600 : X_AND2 
      port map ( I0 => N283 , I1 => N97 , O => U600_2_INV ) ;
    U601 : X_AND2 
      port map ( I0 => N284 , I1 => N98 , O => U601_2_INV ) ;
    U602 : X_AND2 
      port map ( I0 => N629 , I1 => N630 , O => U602_2_INV ) ;
    U603 : X_AND2 
      port map ( I0 => N285 , I1 => N99 , O => U603_2_INV ) ;
    U604 : X_AND2 
      port map ( I0 => N286 , I1 => N100 , O => U604_2_INV ) ;
    U605 : X_AND2 
      port map ( I0 => N631 , I1 => N632 , O => U605_2_INV ) ;
    U606 : X_AND2 
      port map ( I0 => N288 , I1 => N85 , O => U606_2_INV ) ;
    U607 : X_AND2 
      port map ( I0 => N289 , I1 => N86 , O => U607_2_INV ) ;
    U608 : X_AND2 
      port map ( I0 => N633 , I1 => N634 , O => U608_2_INV ) ;
    U609 : X_AND2 
      port map ( I0 => N290 , I1 => N87 , O => U609_2_INV ) ;
    U610 : X_AND2 
      port map ( I0 => N291 , I1 => N88 , O => U610_2_INV ) ;
    U611 : X_AND2 
      port map ( I0 => N635 , I1 => N636 , O => U611_2_INV ) ;
    U612 : X_AND2 
      port map ( I0 => N277 , I1 => N90 , O => U612_2_INV ) ;
    U613 : X_AND2 
      port map ( I0 => N292 , I1 => N89 , O => U613_2_INV ) ;
    U614 : X_AND2 
      port map ( I0 => N637 , I1 => N638 , O => U614_2_INV ) ;
    U615 : X_AND2 
      port map ( I0 => N278 , I1 => N91 , O => U615_2_INV ) ;
    U616 : X_AND2 
      port map ( I0 => N279 , I1 => N92 , O => U616_2_INV ) ;
    U617 : X_AND2 
      port map ( I0 => N639 , I1 => N640 , O => U617_2_INV ) ;
    U618 : X_AND2 
      port map ( I0 => N280 , I1 => N93 , O => U618_2_INV ) ;
    U619 : X_AND2 
      port map ( I0 => N281 , I1 => N94 , O => U619_2_INV ) ;
    U620 : X_AND2 
      port map ( I0 => N641 , I1 => N642 , O => U620_2_INV ) ;
    U621 : X_AND2 
      port map ( I0 => N282 , I1 => N95 , O => U621_2_INV ) ;
    U622 : X_AND2 
      port map ( I0 => N283 , I1 => N96 , O => U622_2_INV ) ;
    U623 : X_AND2 
      port map ( I0 => N643 , I1 => N644 , O => U623_2_INV ) ;
    U624 : X_AND2 
      port map ( I0 => N284 , I1 => N97 , O => U624_2_INV ) ;
    U625 : X_AND2 
      port map ( I0 => N285 , I1 => N98 , O => U625_2_INV ) ;
    U626 : X_AND2 
      port map ( I0 => N645 , I1 => N646 , O => U626_2_INV ) ;
    U627 : X_AND2 
      port map ( I0 => N286 , I1 => N99 , O => U627_2_INV ) ;
    U628 : X_AND2 
      port map ( I0 => N287 , I1 => N100 , O => U628_2_INV ) ;
    U629 : X_AND2 
      port map ( I0 => N647 , I1 => N648 , O => U629_2_INV ) ;
    U630 : X_AND2 
      port map ( I0 => N289 , I1 => N85 , O => U630_2_INV ) ;
    U631 : X_AND2 
      port map ( I0 => N290 , I1 => N86 , O => U631_2_INV ) ;
    U632 : X_AND2 
      port map ( I0 => N649 , I1 => N650 , O => U632_2_INV ) ;
    U633 : X_AND2 
      port map ( I0 => N291 , I1 => N87 , O => U633_2_INV ) ;
    U634 : X_AND2 
      port map ( I0 => N292 , I1 => N88 , O => U634_2_INV ) ;
    U635 : X_AND2 
      port map ( I0 => N651 , I1 => N652 , O => U635_2_INV ) ;
    U636 : X_AND2 
      port map ( I0 => N277 , I1 => N89 , O => U636_2_INV ) ;
    U637 : X_AND2 
      port map ( I0 => N278 , I1 => N90 , O => U637_2_INV ) ;
    U638 : X_AND2 
      port map ( I0 => N653 , I1 => N654 , O => U638_2_INV ) ;
    U639 : X_AND2 
      port map ( I0 => N279 , I1 => N91 , O => U639_2_INV ) ;
    U640 : X_AND2 
      port map ( I0 => N280 , I1 => N92 , O => U640_2_INV ) ;
    U641 : X_AND2 
      port map ( I0 => N655 , I1 => N656 , O => U641_2_INV ) ;
    U642 : X_AND2 
      port map ( I0 => N281 , I1 => N93 , O => U642_2_INV ) ;
    U643 : X_AND2 
      port map ( I0 => N282 , I1 => N94 , O => U643_2_INV ) ;
    U644 : X_AND2 
      port map ( I0 => N657 , I1 => N658 , O => U644_2_INV ) ;
    U645 : X_AND2 
      port map ( I0 => N283 , I1 => N95 , O => U645_2_INV ) ;
    U646 : X_AND2 
      port map ( I0 => N284 , I1 => N96 , O => U646_2_INV ) ;
    U647 : X_AND2 
      port map ( I0 => N659 , I1 => N660 , O => U647_2_INV ) ;
    U648 : X_AND2 
      port map ( I0 => N285 , I1 => N97 , O => U648_2_INV ) ;
    U649 : X_AND2 
      port map ( I0 => N286 , I1 => N98 , O => U649_2_INV ) ;
    U650 : X_AND2 
      port map ( I0 => N661 , I1 => N662 , O => U650_2_INV ) ;
    U651 : X_AND2 
      port map ( I0 => N287 , I1 => N99 , O => U651_2_INV ) ;
    U652 : X_AND2 
      port map ( I0 => N288 , I1 => N100 , O => U652_2_INV ) ;
    U653 : X_AND2 
      port map ( I0 => N663 , I1 => N664 , O => U653_2_INV ) ;
    U654 : X_AND2 
      port map ( I0 => N290 , I1 => N85 , O => U654_2_INV ) ;
    U655 : X_AND2 
      port map ( I0 => N291 , I1 => N86 , O => U655_2_INV ) ;
    U656 : X_AND2 
      port map ( I0 => N665 , I1 => N666 , O => U656_2_INV ) ;
    U657 : X_AND2 
      port map ( I0 => N277 , I1 => N88 , O => U657_2_INV ) ;
    U658 : X_AND2 
      port map ( I0 => N292 , I1 => N87 , O => U658_2_INV ) ;
    U659 : X_AND2 
      port map ( I0 => N667 , I1 => N668 , O => U659_2_INV ) ;
    U660 : X_AND2 
      port map ( I0 => N278 , I1 => N89 , O => U660_2_INV ) ;
    U661 : X_AND2 
      port map ( I0 => N279 , I1 => N90 , O => U661_2_INV ) ;
    U662 : X_AND2 
      port map ( I0 => N669 , I1 => N670 , O => U662_2_INV ) ;
    U663 : X_AND2 
      port map ( I0 => N280 , I1 => N91 , O => U663_2_INV ) ;
    U664 : X_AND2 
      port map ( I0 => N281 , I1 => N92 , O => U664_2_INV ) ;
    U665 : X_AND2 
      port map ( I0 => N671 , I1 => N672 , O => U665_2_INV ) ;
    U666 : X_AND2 
      port map ( I0 => N282 , I1 => N93 , O => U666_2_INV ) ;
    U667 : X_AND2 
      port map ( I0 => N283 , I1 => N94 , O => U667_2_INV ) ;
    U668 : X_AND2 
      port map ( I0 => N673 , I1 => N674 , O => U668_2_INV ) ;
    U669 : X_AND2 
      port map ( I0 => N284 , I1 => N95 , O => U669_2_INV ) ;
    U670 : X_AND2 
      port map ( I0 => N285 , I1 => N96 , O => U670_2_INV ) ;
    U671 : X_AND2 
      port map ( I0 => N675 , I1 => N676 , O => U671_2_INV ) ;
    U672 : X_AND2 
      port map ( I0 => N286 , I1 => N97 , O => U672_2_INV ) ;
    U673 : X_AND2 
      port map ( I0 => N287 , I1 => N98 , O => U673_2_INV ) ;
    U674 : X_AND2 
      port map ( I0 => N677 , I1 => N678 , O => U674_2_INV ) ;
    U675 : X_AND2 
      port map ( I0 => N288 , I1 => N99 , O => U675_2_INV ) ;
    U676 : X_AND2 
      port map ( I0 => N289 , I1 => N100 , O => U676_2_INV ) ;
    U677 : X_AND2 
      port map ( I0 => N679 , I1 => N680 , O => U677_2_INV ) ;
    U678 : X_AND2 
      port map ( I0 => N291 , I1 => N85 , O => U678_2_INV ) ;
    U679 : X_AND2 
      port map ( I0 => N292 , I1 => N86 , O => U679_2_INV ) ;
    U680 : X_AND2 
      port map ( I0 => N681 , I1 => N682 , O => U680_2_INV ) ;
    U681 : X_AND2 
      port map ( I0 => N277 , I1 => N87 , O => U681_2_INV ) ;
    U682 : X_AND2 
      port map ( I0 => N278 , I1 => N88 , O => U682_2_INV ) ;
    U683 : X_AND2 
      port map ( I0 => N683 , I1 => N684 , O => U683_2_INV ) ;
    U684 : X_AND2 
      port map ( I0 => N279 , I1 => N89 , O => U684_2_INV ) ;
    U685 : X_AND2 
      port map ( I0 => N280 , I1 => N90 , O => U685_2_INV ) ;
    U686 : X_AND2 
      port map ( I0 => N685 , I1 => N686 , O => U686_2_INV ) ;
    U687 : X_AND2 
      port map ( I0 => N281 , I1 => N91 , O => U687_2_INV ) ;
    U688 : X_AND2 
      port map ( I0 => N282 , I1 => N92 , O => U688_2_INV ) ;
    U689 : X_AND2 
      port map ( I0 => N687 , I1 => N688 , O => U689_2_INV ) ;
    U690 : X_AND2 
      port map ( I0 => N283 , I1 => N93 , O => U690_2_INV ) ;
    U691 : X_AND2 
      port map ( I0 => N284 , I1 => N94 , O => U691_2_INV ) ;
    U692 : X_AND2 
      port map ( I0 => N689 , I1 => N690 , O => U692_2_INV ) ;
    U693 : X_AND2 
      port map ( I0 => N285 , I1 => N95 , O => U693_2_INV ) ;
    U694 : X_AND2 
      port map ( I0 => N286 , I1 => N96 , O => U694_2_INV ) ;
    U695 : X_AND2 
      port map ( I0 => N691 , I1 => N692 , O => U695_2_INV ) ;
    U696 : X_AND2 
      port map ( I0 => N287 , I1 => N97 , O => U696_2_INV ) ;
    U697 : X_AND2 
      port map ( I0 => N288 , I1 => N98 , O => U697_2_INV ) ;
    U698 : X_AND2 
      port map ( I0 => N693 , I1 => N694 , O => U698_2_INV ) ;
    U699 : X_AND2 
      port map ( I0 => N289 , I1 => N99 , O => U699_2_INV ) ;
    U700 : X_AND2 
      port map ( I0 => N290 , I1 => N100 , O => U700_2_INV ) ;
    U701 : X_AND2 
      port map ( I0 => N695 , I1 => N696 , O => U701_2_INV ) ;
    U702 : X_AND2 
      port map ( I0 => N277 , I1 => N86 , O => U702_2_INV ) ;
    U703 : X_AND2 
      port map ( I0 => N292 , I1 => N85 , O => U703_2_INV ) ;
    U704 : X_AND2 
      port map ( I0 => N697 , I1 => N698 , O => U704_2_INV ) ;