time_sim.vhd

实用的程序代码

    U405 : X_AND2 
      port map ( I0 => N288 , I1 => N95 , O => U405_2_INV ) ;
    U406 : X_AND2 
      port map ( I0 => N289 , I1 => N96 , O => U406_2_INV ) ;
    U407 : X_AND2 
      port map ( I0 => N499 , I1 => N500 , O => U407_2_INV ) ;
    U408 : X_AND2 
      port map ( I0 => N290 , I1 => N97 , O => U408_2_INV ) ;
    U409 : X_AND2 
      port map ( I0 => N291 , I1 => N98 , O => U409_2_INV ) ;
    U410 : X_AND2 
      port map ( I0 => N501 , I1 => N502 , O => U410_2_INV ) ;
    U411 : X_AND2 
      port map ( I0 => N277 , I1 => N100 , O => U411_2_INV ) ;
    U412 : X_AND2 
      port map ( I0 => N292 , I1 => N99 , O => U412_2_INV ) ;
    U413 : X_AND2 
      port map ( I0 => N503 , I1 => N504 , O => U413_2_INV ) ;
    U414 : X_AND2 
      port map ( I0 => N279 , I1 => N85 , O => U414_2_INV ) ;
    U415 : X_AND2 
      port map ( I0 => N280 , I1 => N86 , O => U415_2_INV ) ;
    U416 : X_AND2 
      port map ( I0 => N505 , I1 => N506 , O => U416_2_INV ) ;
    U417 : X_AND2 
      port map ( I0 => N281 , I1 => N87 , O => U417_2_INV ) ;
    U418 : X_AND2 
      port map ( I0 => N282 , I1 => N88 , O => U418_2_INV ) ;
    U419 : X_AND2 
      port map ( I0 => N507 , I1 => N508 , O => U419_2_INV ) ;
    U420 : X_AND2 
      port map ( I0 => N283 , I1 => N89 , O => U420_2_INV ) ;
    U421 : X_AND2 
      port map ( I0 => N284 , I1 => N90 , O => U421_2_INV ) ;
    U422 : X_AND2 
      port map ( I0 => N509 , I1 => N510 , O => U422_2_INV ) ;
    U423 : X_AND2 
      port map ( I0 => N285 , I1 => N91 , O => U423_2_INV ) ;
    U424 : X_AND2 
      port map ( I0 => N286 , I1 => N92 , O => U424_2_INV ) ;
    U425 : X_AND2 
      port map ( I0 => N511 , I1 => N512 , O => U425_2_INV ) ;
    U426 : X_AND2 
      port map ( I0 => N287 , I1 => N93 , O => U426_2_INV ) ;
    U427 : X_AND2 
      port map ( I0 => N288 , I1 => N94 , O => U427_2_INV ) ;
    U428 : X_AND2 
      port map ( I0 => N513 , I1 => N514 , O => U428_2_INV ) ;
    U429 : X_AND2 
      port map ( I0 => N289 , I1 => N95 , O => U429_2_INV ) ;
    U430 : X_AND2 
      port map ( I0 => N290 , I1 => N96 , O => U430_2_INV ) ;
    U431 : X_AND2 
      port map ( I0 => N515 , I1 => N516 , O => U431_2_INV ) ;
    U432 : X_AND2 
      port map ( I0 => N291 , I1 => N97 , O => U432_2_INV ) ;
    U433 : X_AND2 
      port map ( I0 => N292 , I1 => N98 , O => U433_2_INV ) ;
    U434 : X_AND2 
      port map ( I0 => N517 , I1 => N518 , O => U434_2_INV ) ;
    U435 : X_AND2 
      port map ( I0 => N277 , I1 => N99 , O => U435_2_INV ) ;
    U436 : X_AND2 
      port map ( I0 => N278 , I1 => N100 , O => U436_2_INV ) ;
    U437 : X_AND2 
      port map ( I0 => N519 , I1 => N520 , O => U437_2_INV ) ;
    U438 : X_AND2 
      port map ( I0 => N280 , I1 => N85 , O => U438_2_INV ) ;
    U439 : X_AND2 
      port map ( I0 => N281 , I1 => N86 , O => U439_2_INV ) ;
    U440 : X_AND2 
      port map ( I0 => N521 , I1 => N522 , O => U440_2_INV ) ;
    U441 : X_AND2 
      port map ( I0 => N282 , I1 => N87 , O => U441_2_INV ) ;
    U442 : X_AND2 
      port map ( I0 => N283 , I1 => N88 , O => U442_2_INV ) ;
    U443 : X_AND2 
      port map ( I0 => N523 , I1 => N524 , O => U443_2_INV ) ;
    U444 : X_AND2 
      port map ( I0 => N284 , I1 => N89 , O => U444_2_INV ) ;
    U445 : X_AND2 
      port map ( I0 => N285 , I1 => N90 , O => U445_2_INV ) ;
    U446 : X_AND2 
      port map ( I0 => N525 , I1 => N526 , O => U446_2_INV ) ;
    U447 : X_AND2 
      port map ( I0 => N286 , I1 => N91 , O => U447_2_INV ) ;
    U448 : X_AND2 
      port map ( I0 => N287 , I1 => N92 , O => U448_2_INV ) ;
    U449 : X_AND2 
      port map ( I0 => N527 , I1 => N528 , O => U449_2_INV ) ;
    U450 : X_AND2 
      port map ( I0 => N288 , I1 => N93 , O => U450_2_INV ) ;
    U451 : X_AND2 
      port map ( I0 => N289 , I1 => N94 , O => U451_2_INV ) ;
    U452 : X_AND2 
      port map ( I0 => N529 , I1 => N530 , O => U452_2_INV ) ;
    U453 : X_AND2 
      port map ( I0 => N290 , I1 => N95 , O => U453_2_INV ) ;
    U454 : X_AND2 
      port map ( I0 => N291 , I1 => N96 , O => U454_2_INV ) ;
    U455 : X_AND2 
      port map ( I0 => N531 , I1 => N532 , O => U455_2_INV ) ;
    U456 : X_AND2 
      port map ( I0 => N277 , I1 => N98 , O => U456_2_INV ) ;
    U457 : X_AND2 
      port map ( I0 => N292 , I1 => N97 , O => U457_2_INV ) ;
    U458 : X_AND2 
      port map ( I0 => N533 , I1 => N534 , O => U458_2_INV ) ;
    U459 : X_AND2 
      port map ( I0 => N278 , I1 => N99 , O => U459_2_INV ) ;
    U460 : X_AND2 
      port map ( I0 => N279 , I1 => N100 , O => U460_2_INV ) ;
    U461 : X_AND2 
      port map ( I0 => N535 , I1 => N536 , O => U461_2_INV ) ;
    U462 : X_AND2 
      port map ( I0 => N281 , I1 => N85 , O => U462_2_INV ) ;
    U463 : X_AND2 
      port map ( I0 => N282 , I1 => N86 , O => U463_2_INV ) ;
    U464 : X_AND2 
      port map ( I0 => N537 , I1 => N538 , O => U464_2_INV ) ;
    U465 : X_AND2 
      port map ( I0 => N283 , I1 => N87 , O => U465_2_INV ) ;
    U466 : X_AND2 
      port map ( I0 => N284 , I1 => N88 , O => U466_2_INV ) ;
    U467 : X_AND2 
      port map ( I0 => N539 , I1 => N540 , O => U467_2_INV ) ;
    U468 : X_AND2 
      port map ( I0 => N285 , I1 => N89 , O => U468_2_INV ) ;
    U469 : X_AND2 
      port map ( I0 => N286 , I1 => N90 , O => U469_2_INV ) ;
    U470 : X_AND2 
      port map ( I0 => N541 , I1 => N542 , O => U470_2_INV ) ;
    U471 : X_AND2 
      port map ( I0 => N287 , I1 => N91 , O => U471_2_INV ) ;
    U472 : X_AND2 
      port map ( I0 => N288 , I1 => N92 , O => U472_2_INV ) ;
    U473 : X_AND2 
      port map ( I0 => N543 , I1 => N544 , O => U473_2_INV ) ;
    U474 : X_AND2 
      port map ( I0 => N289 , I1 => N93 , O => U474_2_INV ) ;
    U475 : X_AND2 
      port map ( I0 => N290 , I1 => N94 , O => U475_2_INV ) ;
    U476 : X_AND2 
      port map ( I0 => N545 , I1 => N546 , O => U476_2_INV ) ;
    U477 : X_AND2 
      port map ( I0 => N291 , I1 => N95 , O => U477_2_INV ) ;
    U478 : X_AND2 
      port map ( I0 => N292 , I1 => N96 , O => U478_2_INV ) ;
    U479 : X_AND2 
      port map ( I0 => N547 , I1 => N548 , O => U479_2_INV ) ;
    U480 : X_AND2 
      port map ( I0 => N277 , I1 => N97 , O => U480_2_INV ) ;
    U481 : X_AND2 
      port map ( I0 => N278 , I1 => N98 , O => U481_2_INV ) ;
    U482 : X_AND2 
      port map ( I0 => N549 , I1 => N550 , O => U482_2_INV ) ;
    U483 : X_AND2 
      port map ( I0 => N279 , I1 => N99 , O => U483_2_INV ) ;
    U484 : X_AND2 
      port map ( I0 => N280 , I1 => N100 , O => U484_2_INV ) ;
    U485 : X_AND2 
      port map ( I0 => N551 , I1 => N552 , O => U485_2_INV ) ;
    U486 : X_AND2 
      port map ( I0 => N282 , I1 => N85 , O => U486_2_INV ) ;
    U487 : X_AND2 
      port map ( I0 => N283 , I1 => N86 , O => U487_2_INV ) ;
    U488 : X_AND2 
      port map ( I0 => N553 , I1 => N554 , O => U488_2_INV ) ;
    U489 : X_AND2 
      port map ( I0 => N284 , I1 => N87 , O => U489_2_INV ) ;
    U490 : X_AND2 
      port map ( I0 => N285 , I1 => N88 , O => U490_2_INV ) ;
    U491 : X_AND2 
      port map ( I0 => N555 , I1 => N556 , O => U491_2_INV ) ;
    U492 : X_AND2 
      port map ( I0 => N286 , I1 => N89 , O => U492_2_INV ) ;
    U493 : X_AND2 
      port map ( I0 => N287 , I1 => N90 , O => U493_2_INV ) ;
    U494 : X_AND2 
      port map ( I0 => N557 , I1 => N558 , O => U494_2_INV ) ;
    U495 : X_AND2 
      port map ( I0 => N288 , I1 => N91 , O => U495_2_INV ) ;
    U496 : X_AND2 
      port map ( I0 => N289 , I1 => N92 , O => U496_2_INV ) ;
    U497 : X_AND2 
      port map ( I0 => N559 , I1 => N560 , O => U497_2_INV ) ;
    U498 : X_AND2 
      port map ( I0 => N290 , I1 => N93 , O => U498_2_INV ) ;
    U499 : X_AND2 
      port map ( I0 => N291 , I1 => N94 , O => U499_2_INV ) ;
    U500 : X_AND2 
      port map ( I0 => N561 , I1 => N562 , O => U500_2_INV ) ;
    U501 : X_AND2 
      port map ( I0 => N277 , I1 => N96 , O => U501_2_INV ) ;
    U502 : X_AND2 
      port map ( I0 => N292 , I1 => N95 , O => U502_2_INV ) ;
    U503 : X_AND2 
      port map ( I0 => N563 , I1 => N564 , O => U503_2_INV ) ;
    U504 : X_AND2 
      port map ( I0 => N278 , I1 => N97 , O => U504_2_INV ) ;
    U505 : X_AND2 
      port map ( I0 => N279 , I1 => N98 , O => U505_2_INV ) ;
    U506 : X_AND2 
      port map ( I0 => N565 , I1 => N566 , O => U506_2_INV ) ;
    U507 : X_AND2 
      port map ( I0 => N280 , I1 => N99 , O => U507_2_INV ) ;
    U508 : X_AND2 
      port map ( I0 => N281 , I1 => N100 , O => U508_2_INV ) ;
    U509 : X_AND2 
      port map ( I0 => N567 , I1 => N568 , O => U509_2_INV ) ;
    U510 : X_AND2 
      port map ( I0 => N283 , I1 => N85 , O => U510_2_INV ) ;
    U511 : X_AND2 
      port map ( I0 => N284 , I1 => N86 , O => U511_2_INV ) ;
    U512 : X_AND2 
      port map ( I0 => N569 , I1 => N570 , O => U512_2_INV ) ;
    U513 : X_AND2 
      port map ( I0 => N285 , I1 => N87 , O => U513_2_INV ) ;
    U514 : X_AND2 
      port map ( I0 => N286 , I1 => N88 , O => U514_2_INV ) ;
    U515 : X_AND2 
      port map ( I0 => N571 , I1 => N572 , O => U515_2_INV ) ;
    U516 : X_AND2 
      port map ( I0 => N287 , I1 => N89 , O => U516_2_INV ) ;
    U517 : X_AND2 
      port map ( I0 => N288 , I1 => N90 , O => U517_2_INV ) ;
    U518 : X_AND2 
      port map ( I0 => N573 , I1 => N574 , O => U518_2_INV ) ;
    U519 : X_AND2 
      port map ( I0 => N289 , I1 => N91 , O => U519_2_INV ) ;
    U520 : X_AND2 
      port map ( I0 => N290 , I1 => N92 , O => U520_2_INV ) ;
    U521 : X_AND2 
      port map ( I0 => N575 , I1 => N576 , O => U521_2_INV ) ;
    U522 : X_AND2 
      port map ( I0 => N291 , I1 => N93 , O => U522_2_INV ) ;
    U523 : X_AND2 
      port map ( I0 => N292 , I1 => N94 , O => U523_2_INV ) ;
    U524 : X_AND2 
      port map ( I0 => N577 , I1 => N578 , O => U524_2_INV ) ;
    U525 : X_AND2 
      port map ( I0 => N277 , I1 => N95 , O => U525_2_INV ) ;
    U526 : X_AND2 
      port map ( I0 => N278 , I1 => N96 , O => U526_2_INV ) ;
    U527 : X_AND2 
      port map ( I0 => N579 , I1 => N580 , O => U527_2_INV ) ;
    U528 : X_AND2 
      port map ( I0 => N279 , I1 => N97 , O => U528_2_INV ) ;
    U529 : X_AND2 
      port map ( I0 => N280 , I1 => N98 , O => U529_2_INV ) ;
    U530 : X_AND2 
      port map ( I0 => N581 , I1 => N582 , O => U530_2_INV ) ;
    U531 : X_AND2 
      port map ( I0 => N281 , I1 => N99 , O => U531_2_INV ) ;
    U532 : X_AND2 
      port map ( I0 => N282 , I1 => N100 , O => U532_2_INV ) ;
    U533 : X_AND2 
      port map ( I0 => N583 , I1 => N584 , O => U533_2_INV ) ;
    U534 : X_AND2 
      port map ( I0 => N285 , I1 => N85 , O => U534_2_INV ) ;
    U535 : X_AND2 
      port map ( I0 => N286 , I1 => N86 , O => U535_2_INV ) ;
    U536 : X_AND2 
      port map ( I0 => N585 , I1 => N586 , O => U536_2_INV ) ;
    U537 : X_AND2 
      port map ( I0 => N287 , I1 => N87 , O => U537_2_INV ) ;
    U538 : X_AND2 
      port map ( I0 => N288 , I1 => N88 , O => U538_2_INV ) ;
    U539 : X_AND2 
      port map ( I0 => N587 , I1 => N588 , O => U539_2_INV ) ;
    U540 : X_AND2 
      port map ( I0 => N289 , I1 => N89 , O => U540_2_INV ) ;
    U541 : X_AND2 
      port map ( I0 => N290 , I1 => N90 , O => U541_2_INV ) ;
    U542 : X_AND2 
      port map ( I0 => N589 , I1 => N590 , O => U542_2_INV ) ;
    U543 : X_AND2 
      port map ( I0 => N291 , I1 => N91 , O => U543_2_INV ) ;
    U544 : X_AND2 
      port map ( I0 => N292 , I1 => N92 , O => U544_2_INV ) ;
    U545 : X_AND2 
      port map ( I0 => N591 , I1 => N592 , O => U545_2_INV ) ;
    U546 : X_AND2 
      port map ( I0 => N277 , I1 => N93 , O => U546_2_INV ) ;
    U547 : X_AND2 
      port map ( I0 => N278 , I1 => N94 , O => U547_2_INV ) ;
    U548 : X_AND2 
      port map ( I0 => N593 , I1 => N594 , O => U548_2_INV ) ;
    U549 : X_AND2 
      port map ( I0 => N279 , I1 => N95 , O => U549_2_INV ) ;
    U550 : X_AND2 
      port map ( I0 => N280 , I1 => N96 , O => U550_2_INV ) ;
    U551 : X_AND2 
      port map ( I0 => N595 , I1 => N596 , O => U551_2_INV ) ;
    U552 : X_AND2 
      port map ( I0 => N281 , I1 => N97 , O => U552_2_INV ) ;
    U553 : X_AND2 
      port map ( I0 => N282 , I1 => N98 , O => U553_2_INV ) ;
    U554 : X_AND2 
      port map ( I0 => N597 , I1 => N598 , O => U554_2_INV ) ;