time_sim.vhd

实用的程序代码

    U522_N533_2_0 : X_OR2 
      port map ( I0 => N530 , I1 => N89 , O => U522_2_0 ) ;
    U522_N533 : X_OR2 
      port map ( I0 => U522_2_0 , I1 => N531 , O => N533 ) ;
    U523_N532_2_0 : X_AND2 
      port map ( I0 => N89 , I1 => N91 , O => U523_2_0 ) ;
    U523_N532 : X_AND2 
      port map ( I0 => U523_2_0 , I1 => N531 , O => U523_N532_2_INV ) ;
    U529_N543_2_0 : X_OR2 
      port map ( I0 => N88 , I1 => N538 , O => U529_2_0 ) ;
    U529_N543 : X_OR2 
      port map ( I0 => U529_2_0 , I1 => N537 , O => U529_N543_2_INV ) ;
    U533_N542_2_0 : X_AND2 
      port map ( I0 => N541 , I1 => N540 , O => U533_2_0 ) ;
    U533_N542 : X_AND2 
      port map ( I0 => U533_2_0 , I1 => N88 , O => N542 ) ;
    U538_N551_2_0 : X_OR2 
      port map ( I0 => N88 , I1 => N546 , O => U538_2_0 ) ;
    U538_N551 : X_OR2 
      port map ( I0 => U538_2_0 , I1 => N545 , O => U538_N551_2_INV ) ;
    U542_N550_2_0 : X_AND2 
      port map ( I0 => N549 , I1 => N548 , O => U542_2_0 ) ;
    U542_N550 : X_AND2 
      port map ( I0 => U542_2_0 , I1 => N88 , O => N550 ) ;
    U547_N559_2_0 : X_AND2 
      port map ( I0 => N554 , I1 => N553 , O => U547_2_0 ) ;
    U547_N559 : X_AND2 
      port map ( I0 => U547_2_0 , I1 => N88 , O => N559 ) ;
    U551_N558_2_0 : X_OR2 
      port map ( I0 => N88 , I1 => N557 , O => U551_2_0 ) ;
    U551_N558 : X_OR2 
      port map ( I0 => U551_2_0 , I1 => N556 , O => U551_N558_2_INV ) ;
    U256_2_INV_16 : X_INV 
      port map ( I => U256_2_INV , O => N296 ) ;
    U261_2_INV_17 : X_INV 
      port map ( I => U261_2_INV , O => N299 ) ;
    U266_2_INV_18 : X_INV 
      port map ( I => U266_2_INV , O => N304 ) ;
    U269_2_INV_19 : X_INV 
      port map ( I => U269_2_INV , O => N307 ) ;
    U275_2_INV_20 : X_INV 
      port map ( I => U275_2_INV , O => N312 ) ;
    U278_2_INV_21 : X_INV 
      port map ( I => U278_2_INV , O => N315 ) ;
    U285_2_INV_22 : X_INV 
      port map ( I => U285_2_INV , O => N326 ) ;
    U290_2_INV_23 : X_INV 
      port map ( I => U290_2_INV , O => N325 ) ;
    U295_2_INV_24 : X_INV 
      port map ( I => U295_2_INV , O => N335 ) ;
    U300_2_INV_25 : X_INV 
      port map ( I => U300_2_INV , O => N334 ) ;
    U305_2_INV_26 : X_INV 
      port map ( I => U305_2_INV , O => N344 ) ;
    U310_2_INV_27 : X_INV 
      port map ( I => U310_2_INV , O => N343 ) ;
    U315_2_INV_28 : X_INV 
      port map ( I => U315_2_INV , O => N353 ) ;
    U320_2_INV_29 : X_INV 
      port map ( I => U320_2_INV , O => N352 ) ;
    U323_2_INV_30 : X_INV 
      port map ( I => U323_2_INV , O => N356 ) ;
    U328_2_INV_31 : X_INV 
      port map ( I => U328_2_INV , O => N359 ) ;
    U332_2_INV_32 : X_INV 
      port map ( I => U332_2_INV , O => N364 ) ;
    U337_2_INV_33 : X_INV 
      port map ( I => U337_2_INV , O => N367 ) ;
    U342_2_INV_34 : X_INV 
      port map ( I => U342_2_INV , O => N372 ) ;
    U345_2_INV_35 : X_INV 
      port map ( I => U345_2_INV , O => N375 ) ;
    U352_2_INV_36 : X_INV 
      port map ( I => U352_2_INV , O => N386 ) ;
    U357_2_INV_37 : X_INV 
      port map ( I => U357_2_INV , O => N385 ) ;
    U363_2_INV_38 : X_INV 
      port map ( I => U363_2_INV , O => N395 ) ;
    U367_2_INV_39 : X_INV 
      port map ( I => U367_2_INV , O => N394 ) ;
    U373_2_INV_40 : X_INV 
      port map ( I => U373_2_INV , O => N404 ) ;
    U377_2_INV_41 : X_INV 
      port map ( I => U377_2_INV , O => N403 ) ;
    U378_2_INV_42 : X_INV 
      port map ( I => U378_2_INV , O => N241 ) ;
    U380_2_INV_43 : X_INV 
      port map ( I => U380_2_INV , O => N406 ) ;
    U381_2_INV_44 : X_INV 
      port map ( I => U381_2_INV , O => N407 ) ;
    U384_2_INV_45 : X_INV 
      port map ( I => U384_2_INV , O => N410 ) ;
    U387_2_INV_46 : X_INV 
      port map ( I => U387_2_INV , O => N240 ) ;
    U389_2_INV_47 : X_INV 
      port map ( I => U389_2_INV , O => N414 ) ;
    U390_2_INV_48 : X_INV 
      port map ( I => U390_2_INV , O => N415 ) ;
    U393_2_INV_49 : X_INV 
      port map ( I => U393_2_INV , O => N418 ) ;
    U396_2_INV_50 : X_INV 
      port map ( I => U396_2_INV , O => N239 ) ;
    U398_2_INV_51 : X_INV 
      port map ( I => U398_2_INV , O => N423 ) ;
    U402_2_INV_52 : X_INV 
      port map ( I => U402_2_INV , O => N425 ) ;
    U403_2_INV_53 : X_INV 
      port map ( I => U403_2_INV , O => N426 ) ;
    U405_2_INV_54 : X_INV 
      port map ( I => U405_2_INV , O => N238 ) ;
    U407_2_INV_55 : X_INV 
      port map ( I => U407_2_INV , O => N430 ) ;
    U408_2_INV_56 : X_INV 
      port map ( I => U408_2_INV , O => N431 ) ;
    U411_2_INV_57 : X_INV 
      port map ( I => U411_2_INV , O => N434 ) ;
    U419_2_INV_58 : X_INV 
      port map ( I => U419_2_INV , O => N445 ) ;
    U423_2_INV_59 : X_INV 
      port map ( I => U423_2_INV , O => N444 ) ;
    U424_2_INV_60 : X_INV 
      port map ( I => U424_2_INV , O => N237 ) ;
    U428_2_INV_61 : X_INV 
      port map ( I => U428_2_INV , O => N454 ) ;
    U433_2_INV_62 : X_INV 
      port map ( I => U433_2_INV , O => N453 ) ;
    U434_2_INV_63 : X_INV 
      port map ( I => U434_2_INV , O => N236 ) ;
    U436_2_INV_64 : X_INV 
      port map ( I => U436_2_INV , O => N457 ) ;
    U440_2_INV_65 : X_INV 
      port map ( I => U440_2_INV , O => N459 ) ;
    U441_2_INV_66 : X_INV 
      port map ( I => U441_2_INV , O => N460 ) ;
    U443_2_INV_67 : X_INV 
      port map ( I => U443_2_INV , O => N235 ) ;
    U445_2_INV_68 : X_INV 
      port map ( I => U445_2_INV , O => N465 ) ;
    U449_2_INV_69 : X_INV 
      port map ( I => U449_2_INV , O => N467 ) ;
    U450_2_INV_70 : X_INV 
      port map ( I => U450_2_INV , O => N468 ) ;
    U452_2_INV_71 : X_INV 
      port map ( I => U452_2_INV , O => N234 ) ;
    U454_2_INV_72 : X_INV 
      port map ( I => U454_2_INV , O => N472 ) ;
    U455_2_INV_73 : X_INV 
      port map ( I => U455_2_INV , O => N473 ) ;
    U458_2_INV_74 : X_INV 
      port map ( I => U458_2_INV , O => N476 ) ;
    U464_2_INV_75 : X_INV 
      port map ( I => U464_2_INV , O => N481 ) ;
    U467_2_INV_76 : X_INV 
      port map ( I => U467_2_INV , O => N484 ) ;
    U470_2_INV_77 : X_INV 
      port map ( I => U470_2_INV , O => N233 ) ;
    U472_2_INV_78 : X_INV 
      port map ( I => U472_2_INV , O => N489 ) ;
    U476_2_INV_79 : X_INV 
      port map ( I => U476_2_INV , O => N491 ) ;
    U477_2_INV_80 : X_INV 
      port map ( I => U477_2_INV , O => N492 ) ;
    U479_2_INV_81 : X_INV 
      port map ( I => U479_2_INV , O => N232 ) ;
    U481_2_INV_82 : X_INV 
      port map ( I => U481_2_INV , O => N496 ) ;
    U482_2_INV_83 : X_INV 
      port map ( I => U482_2_INV , O => N497 ) ;
    U485_2_INV_84 : X_INV 
      port map ( I => U485_2_INV , O => N500 ) ;
    U488_2_INV_85 : X_INV 
      port map ( I => U488_2_INV , O => N231 ) ;
    U490_2_INV_86 : X_INV 
      port map ( I => U490_2_INV , O => N505 ) ;
    U494_2_INV_87 : X_INV 
      port map ( I => U494_2_INV , O => N507 ) ;
    U495_2_INV_88 : X_INV 
      port map ( I => U495_2_INV , O => N508 ) ;
    U497_2_INV_89 : X_INV 
      port map ( I => U497_2_INV , O => N230 ) ;
    U499_2_INV_90 : X_INV 
      port map ( I => U499_2_INV , O => N512 ) ;
    U500_2_INV_91 : X_INV 
      port map ( I => U500_2_INV , O => N513 ) ;
    U503_2_INV_92 : X_INV 
      port map ( I => U503_2_INV , O => N516 ) ;
    U508_2_INV_93 : X_INV 
      port map ( I => U508_2_INV , O => N521 ) ;
    U513_2_INV_94 : X_INV 
      port map ( I => U513_2_INV , O => N524 ) ;
    U515_2_INV_95 : X_INV 
      port map ( I => U515_2_INV , O => N229 ) ;
    U519_2_INV_96 : X_INV 
      port map ( I => U519_2_INV , O => N535 ) ;
    U524_2_INV_97 : X_INV 
      port map ( I => U524_2_INV , O => N534 ) ;
    U525_2_INV_98 : X_INV 
      port map ( I => U525_2_INV , O => N228 ) ;
    U527_2_INV_99 : X_INV 
      port map ( I => U527_2_INV , O => N537 ) ;
    U528_2_INV_100 : X_INV 
      port map ( I => U528_2_INV , O => N538 ) ;
    U531_2_INV_101 : X_INV 
      port map ( I => U531_2_INV , O => N541 ) ;
    U534_2_INV_102 : X_INV 
      port map ( I => U534_2_INV , O => N227 ) ;
    U536_2_INV_103 : X_INV 
      port map ( I => U536_2_INV , O => N545 ) ;
    U537_2_INV_104 : X_INV 
      port map ( I => U537_2_INV , O => N546 ) ;
    U540_2_INV_105 : X_INV 
      port map ( I => U540_2_INV , O => N549 ) ;
    U543_2_INV_106 : X_INV 
      port map ( I => U543_2_INV , O => N226 ) ;
    U545_2_INV_107 : X_INV 
      port map ( I => U545_2_INV , O => N554 ) ;
    U549_2_INV_108 : X_INV 
      port map ( I => U549_2_INV , O => N556 ) ;
    U550_2_INV_109 : X_INV 
      port map ( I => U550_2_INV , O => N557 ) ;
    U262_N300_2_INV_110 : X_INV 
      port map ( I => U262_N300_2_INV , O => N300 ) ;
    U267_N309_2_INV_111 : X_INV 
      port map ( I => U267_N309_2_INV , O => N309 ) ;
    U276_N317_2_INV_112 : X_INV 
      port map ( I => U276_N317_2_INV , O => N317 ) ;
    U284_N319_2_INV_113 : X_INV 
      port map ( I => U284_N319_2_INV , O => N319 ) ;
    U294_N328_2_INV_114 : X_INV 
      port map ( I => U294_N328_2_INV , O => N328 ) ;
    U304_N337_2_INV_115 : X_INV 
      port map ( I => U304_N337_2_INV , O => N337 ) ;
    U314_N346_2_INV_116 : X_INV 
      port map ( I => U314_N346_2_INV , O => N346 ) ;
    U329_N360_2_INV_117 : X_INV 
      port map ( I => U329_N360_2_INV , O => N360 ) ;
    U338_N368_2_INV_118 : X_INV 
      port map ( I => U338_N368_2_INV , O => N368 ) ;
    U343_N377_2_INV_119 : X_INV 
      port map ( I => U343_N377_2_INV , O => N377 ) ;
    U351_N379_2_INV_120 : X_INV 
      port map ( I => U351_N379_2_INV , O => N379 ) ;
    U366_N392_2_INV_121 : X_INV 
      port map ( I => U366_N392_2_INV , O => N392 ) ;
    U376_N401_2_INV_122 : X_INV 
      port map ( I => U376_N401_2_INV , O => N401 ) ;
    U382_N412_2_INV_123 : X_INV 
      port map ( I => U382_N412_2_INV , O => N412 ) ;
    U391_N420_2_INV_124 : X_INV 
      port map ( I => U391_N420_2_INV , O => N420 ) ;
    U404_N427_2_INV_125 : X_INV 
      port map ( I => U404_N427_2_INV , O => N427 ) ;
    U409_N436_2_INV_126 : X_INV 
      port map ( I => U409_N436_2_INV , O => N436 ) ;
    U422_N442_2_INV_127 : X_INV 
      port map ( I => U422_N442_2_INV , O => N442 ) ;
    U427_N447_2_INV_128 : X_INV 
      port map ( I => U427_N447_2_INV , O => N447 ) ;
    U432_N451_2_INV_129 : X_INV 
      port map ( I => U432_N451_2_INV , O => N451 ) ;
    U442_N461_2_INV_130 : X_INV 
      port map ( I => U442_N461_2_INV , O => N461 ) ;
    U451_N469_2_INV_131 : X_INV 
      port map ( I => U451_N469_2_INV , O => N469 ) ;
    U456_N478_2_INV_132 : X_INV 
      port map ( I => U456_N478_2_INV , O => N478 ) ;
    U465_N486_2_INV_133 : X_INV 
      port map ( I => U465_N486_2_INV , O => N486 ) ;
    U478_N493_2_INV_134 : X_INV 
      port map ( I => U478_N493_2_INV , O => N493 ) ;
    U483_N502_2_INV_135 : X_INV 
      port map ( I => U483_N502_2_INV , O => N502 ) ;
    U496_N509_2_INV_136 : X_INV 
      port map ( I => U496_N509_2_INV , O => N509 ) ;
    U501_N518_2_INV_137 : X_INV 
      port map ( I => U501_N518_2_INV , O => N518 ) ;
    U514_N525_2_INV_138 : X_INV 
      port map ( I => U514_N525_2_INV , O => N525 ) ;
    U518_N528_2_INV_139 : X_INV 
      port map ( I => U518_N528_2_INV , O => N528 ) ;
    U523_N532_2_INV_140 : X_INV 
      port map ( I => U523_N532_2_INV , O => N532 ) ;
    U529_N543_2_INV_141 : X_INV 
      port map ( I => U529_N543_2_INV , O => N543 ) ;
    U538_N551_2_INV_142 : X_INV 
      port map ( I => U538_N551_2_INV , O => N551 ) ;
    U551_N558_2_INV_143 : X_INV 
      port map ( I => U551_N558_2_INV , O => N558 ) ;
    U238_1I20_GTS_TRI_2_INV_144 : X_INV 
      port map ( I => GTS , O => U238_1I20_GTS_TRI_2_INV ) ;
    U239_1I20_GTS_TRI_2_INV_145 : X_INV 
      port map ( I => GTS , O => U239_1I20_GTS_TRI_2_INV ) ;
    U240_1I20_GTS_TRI_2_INV_146 : X_INV 
      port map ( I => GTS , O => U240_1I20_GTS_TRI_2_INV ) ;
    U241_1I20_GTS_TRI_2_INV_147 : X_INV 
      port map ( I => GTS , O => U241_1I20_GTS_TRI_2_INV ) ;
    U242_1I20_GTS_TRI_2_INV_148 : X_INV 
      port map ( I => GTS , O => U242_1I20_GTS_TRI_2_INV ) ;
    U243_1I20_GTS_TRI_2_INV_149 : X_INV 
      port map ( I => GTS , O => U243_1I20_GTS_TRI_2_INV ) ;
    U244_1I20_GTS_TRI_2_INV_150 : X_INV 
      port map ( I => GTS , O => U244_1I20_GTS_TRI_2_INV ) ;
    U245_1I20_GTS_TRI_2_INV_151 : X_INV 
      port map ( I => GTS , O => U245_1I20_GTS_TRI_2_INV ) ;
    U246_1I20_GTS_TRI_2_INV_152 : X_INV 
      port map ( I => GTS , O => U246_1I20_GTS_TRI_2_INV ) ;
    U247_1I20_GTS_TRI_2_INV_153 : X_INV 
      port map ( I => GTS , O => U247_1I20_GTS_TRI_2_INV ) ;
    U248_1I20_GTS_TRI_2_INV_154 : X_INV 
      port map ( I => GTS , O => U248_1I20_GTS_TRI_2_INV ) ;
    U249_1I20_GTS_TRI_2_INV_155 : X_INV 
      port map ( I => GTS , O => U249_1I20_GTS_TRI_2_INV ) ;
    U250_1I20_GTS_TRI_2_INV_156 : X_INV 
      port map ( I => GTS , O => U250_1I20_GTS_TRI_2_INV ) ;
    U251_1I20_GTS_TRI_2_INV_157 : X_INV 
      port map ( I => GTS , O => U251_1I20_GTS_TRI_2_INV ) ;
    U252_1I20_GTS_TRI_2_INV_158 : X_INV 
      port map ( I => GTS , O => U252_1I20_GTS_TRI_2_INV ) ;
    U253_1I20_GTS_TRI_2_INV_159 : X_INV 
      port map ( I => GTS , O => U253_1I20_GTS_TRI_2_INV ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;