time_sim.vhd

实用的程序代码

      CTL => U249_1I20_GTS_TRI_2_INV ) ;
    U250_1I20 : X_BUF 
      port map ( I => N572 , O => U250_1I20_GTS_TRI ) ;
    U250_1I20_GTS_TRI_12 : X_TRI 
      port map ( I => U250_1I20_GTS_TRI , O => B_P(3) , 
      CTL => U250_1I20_GTS_TRI_2_INV ) ;
    U251_1I20 : X_BUF 
      port map ( I => N573 , O => U251_1I20_GTS_TRI ) ;
    U251_1I20_GTS_TRI_13 : X_TRI 
      port map ( I => U251_1I20_GTS_TRI , O => B_P(2) , 
      CTL => U251_1I20_GTS_TRI_2_INV ) ;
    U252_1I20 : X_BUF 
      port map ( I => N574 , O => U252_1I20_GTS_TRI ) ;
    U252_1I20_GTS_TRI_14 : X_TRI 
      port map ( I => U252_1I20_GTS_TRI , O => B_P(1) , 
      CTL => U252_1I20_GTS_TRI_2_INV ) ;
    U253_1I20 : X_BUF 
      port map ( I => N575 , O => U253_1I20_GTS_TRI ) ;
    U253_1I20_GTS_TRI_15 : X_TRI 
      port map ( I => U253_1I20_GTS_TRI , O => B_P(0) , 
      CTL => U253_1I20_GTS_TRI_2_INV ) ;
    U258_N301_2_0 : X_AND2 
      port map ( I0 => N296 , I1 => N295 , O => U258_2_0 ) ;
    U258_N301 : X_AND2 
      port map ( I0 => U258_2_0 , I1 => N86 , O => N301 ) ;
    U262_N300_2_0 : X_OR2 
      port map ( I0 => N86 , I1 => N299 , O => U262_2_0 ) ;
    U262_N300 : X_OR2 
      port map ( I0 => U262_2_0 , I1 => N298 , O => U262_N300_2_INV ) ;
    U267_N309_2_0 : X_OR2 
      port map ( I0 => N86 , I1 => N304 , O => U267_2_0 ) ;
    U267_N309 : X_OR2 
      port map ( I0 => U267_2_0 , I1 => N303 , O => U267_N309_2_INV ) ;
    U271_N308_2_0 : X_AND2 
      port map ( I0 => N307 , I1 => N306 , O => U271_2_0 ) ;
    U271_N308 : X_AND2 
      port map ( I0 => U271_2_0 , I1 => N86 , O => N308 ) ;
    U276_N317_2_0 : X_OR2 
      port map ( I0 => N86 , I1 => N312 , O => U276_2_0 ) ;
    U276_N317 : X_OR2 
      port map ( I0 => U276_2_0 , I1 => N311 , O => U276_N317_2_INV ) ;
    U280_N316_2_0 : X_AND2 
      port map ( I0 => N315 , I1 => N314 , O => U280_2_0 ) ;
    U280_N316 : X_AND2 
      port map ( I0 => U280_2_0 , I1 => N86 , O => N316 ) ;
    U283_N320_2_0 : X_OR2 
      port map ( I0 => N86 , I1 => N233 , O => U283_2_0 ) ;
    U283_N320 : X_OR2 
      port map ( I0 => U283_2_0 , I1 => N87 , O => N320 ) ;
    U284_N319_2_0 : X_AND2 
      port map ( I0 => N318 , I1 => N86 , O => U284_2_0 ) ;
    U284_N319 : X_AND2 
      port map ( I0 => U284_2_0 , I1 => N87 , O => U284_N319_2_INV ) ;
    U288_N324_2_0 : X_OR2 
      port map ( I0 => N87 , I1 => N231 , O => U288_2_0 ) ;
    U288_N324 : X_OR2 
      port map ( I0 => U288_2_0 , I1 => N321 , O => N324 ) ;
    U289_N323_2_0 : X_OR2 
      port map ( I0 => N230 , I1 => N322 , O => U289_2_0 ) ;
    U289_N323 : X_OR2 
      port map ( I0 => U289_2_0 , I1 => N86 , O => N323 ) ;
    U293_N329_2_0 : X_OR2 
      port map ( I0 => N86 , I1 => N229 , O => U293_2_0 ) ;
    U293_N329 : X_OR2 
      port map ( I0 => U293_2_0 , I1 => N87 , O => N329 ) ;
    U294_N328_2_0 : X_AND2 
      port map ( I0 => N327 , I1 => N86 , O => U294_2_0 ) ;
    U294_N328 : X_AND2 
      port map ( I0 => U294_2_0 , I1 => N87 , O => U294_N328_2_INV ) ;
    U298_N333_2_0 : X_OR2 
      port map ( I0 => N87 , I1 => N227 , O => U298_2_0 ) ;
    U298_N333 : X_OR2 
      port map ( I0 => U298_2_0 , I1 => N330 , O => N333 ) ;
    U299_N332_2_0 : X_OR2 
      port map ( I0 => N226 , I1 => N331 , O => U299_2_0 ) ;
    U299_N332 : X_OR2 
      port map ( I0 => U299_2_0 , I1 => N86 , O => N332 ) ;
    U303_N338_2_0 : X_OR2 
      port map ( I0 => N86 , I1 => N241 , O => U303_2_0 ) ;
    U303_N338 : X_OR2 
      port map ( I0 => U303_2_0 , I1 => N87 , O => N338 ) ;
    U304_N337_2_0 : X_AND2 
      port map ( I0 => N336 , I1 => N86 , O => U304_2_0 ) ;
    U304_N337 : X_AND2 
      port map ( I0 => U304_2_0 , I1 => N87 , O => U304_N337_2_INV ) ;
    U308_N342_2_0 : X_OR2 
      port map ( I0 => N87 , I1 => N239 , O => U308_2_0 ) ;
    U308_N342 : X_OR2 
      port map ( I0 => U308_2_0 , I1 => N339 , O => N342 ) ;
    U309_N341_2_0 : X_OR2 
      port map ( I0 => N238 , I1 => N340 , O => U309_2_0 ) ;
    U309_N341 : X_OR2 
      port map ( I0 => U309_2_0 , I1 => N86 , O => N341 ) ;
    U313_N347_2_0 : X_OR2 
      port map ( I0 => N86 , I1 => N237 , O => U313_2_0 ) ;
    U313_N347 : X_OR2 
      port map ( I0 => U313_2_0 , I1 => N87 , O => N347 ) ;
    U314_N346_2_0 : X_AND2 
      port map ( I0 => N345 , I1 => N86 , O => U314_2_0 ) ;
    U314_N346 : X_AND2 
      port map ( I0 => U314_2_0 , I1 => N87 , O => U314_N346_2_INV ) ;
    U318_N351_2_0 : X_OR2 
      port map ( I0 => N87 , I1 => N235 , O => U318_2_0 ) ;
    U318_N351 : X_OR2 
      port map ( I0 => U318_2_0 , I1 => N348 , O => N351 ) ;
    U319_N350_2_0 : X_OR2 
      port map ( I0 => N234 , I1 => N349 , O => U319_2_0 ) ;
    U319_N350 : X_OR2 
      port map ( I0 => U319_2_0 , I1 => N86 , O => N350 ) ;
    U325_N361_2_0 : X_AND2 
      port map ( I0 => N356 , I1 => N355 , O => U325_2_0 ) ;
    U325_N361 : X_AND2 
      port map ( I0 => U325_2_0 , I1 => N86 , O => N361 ) ;
    U329_N360_2_0 : X_OR2 
      port map ( I0 => N86 , I1 => N359 , O => U329_2_0 ) ;
    U329_N360 : X_OR2 
      port map ( I0 => U329_2_0 , I1 => N358 , O => U329_N360_2_INV ) ;
    U334_N369_2_0 : X_AND2 
      port map ( I0 => N364 , I1 => N363 , O => U334_2_0 ) ;
    U334_N369 : X_AND2 
      port map ( I0 => U334_2_0 , I1 => N86 , O => N369 ) ;
    U338_N368_2_0 : X_OR2 
      port map ( I0 => N86 , I1 => N367 , O => U338_2_0 ) ;
    U338_N368 : X_OR2 
      port map ( I0 => U338_2_0 , I1 => N366 , O => U338_N368_2_INV ) ;
    U343_N377_2_0 : X_OR2 
      port map ( I0 => N86 , I1 => N372 , O => U343_2_0 ) ;
    U343_N377 : X_OR2 
      port map ( I0 => U343_2_0 , I1 => N371 , O => U343_N377_2_INV ) ;
    U347_N376_2_0 : X_AND2 
      port map ( I0 => N375 , I1 => N374 , O => U347_2_0 ) ;
    U347_N376 : X_AND2 
      port map ( I0 => U347_2_0 , I1 => N86 , O => N376 ) ;
    U350_N380_2_0 : X_OR2 
      port map ( I0 => N86 , I1 => N231 , O => U350_2_0 ) ;
    U350_N380 : X_OR2 
      port map ( I0 => U350_2_0 , I1 => N87 , O => N380 ) ;
    U351_N379_2_0 : X_AND2 
      port map ( I0 => N378 , I1 => N86 , O => U351_2_0 ) ;
    U351_N379 : X_AND2 
      port map ( I0 => U351_2_0 , I1 => N87 , O => U351_N379_2_INV ) ;
    U355_N384_2_0 : X_OR2 
      port map ( I0 => N87 , I1 => N233 , O => U355_2_0 ) ;
    U355_N384 : X_OR2 
      port map ( I0 => U355_2_0 , I1 => N381 , O => N384 ) ;
    U356_N383_2_0 : X_OR2 
      port map ( I0 => N232 , I1 => N382 , O => U356_2_0 ) ;
    U356_N383 : X_OR2 
      port map ( I0 => U356_2_0 , I1 => N86 , O => N383 ) ;
    U361_N390_2_0 : X_OR2 
      port map ( I0 => N87 , I1 => N229 , O => U361_2_0 ) ;
    U361_N390 : X_OR2 
      port map ( I0 => U361_2_0 , I1 => N387 , O => N390 ) ;
    U362_N389_2_0 : X_OR2 
      port map ( I0 => N228 , I1 => N388 , O => U362_2_0 ) ;
    U362_N389 : X_OR2 
      port map ( I0 => U362_2_0 , I1 => N86 , O => N389 ) ;
    U365_N393_2_0 : X_OR2 
      port map ( I0 => N86 , I1 => N227 , O => U365_2_0 ) ;
    U365_N393 : X_OR2 
      port map ( I0 => U365_2_0 , I1 => N87 , O => N393 ) ;
    U366_N392_2_0 : X_AND2 
      port map ( I0 => N391 , I1 => N86 , O => U366_2_0 ) ;
    U366_N392 : X_AND2 
      port map ( I0 => U366_2_0 , I1 => N87 , O => U366_N392_2_INV ) ;
    U371_N399_2_0 : X_OR2 
      port map ( I0 => N87 , I1 => N241 , O => U371_2_0 ) ;
    U371_N399 : X_OR2 
      port map ( I0 => U371_2_0 , I1 => N396 , O => N399 ) ;
    U372_N398_2_0 : X_OR2 
      port map ( I0 => N240 , I1 => N397 , O => U372_2_0 ) ;
    U372_N398 : X_OR2 
      port map ( I0 => U372_2_0 , I1 => N86 , O => N398 ) ;
    U375_N402_2_0 : X_OR2 
      port map ( I0 => N86 , I1 => N239 , O => U375_2_0 ) ;
    U375_N402 : X_OR2 
      port map ( I0 => U375_2_0 , I1 => N87 , O => N402 ) ;
    U376_N401_2_0 : X_AND2 
      port map ( I0 => N400 , I1 => N86 , O => U376_2_0 ) ;
    U376_N401 : X_AND2 
      port map ( I0 => U376_2_0 , I1 => N87 , O => U376_N401_2_INV ) ;
    U382_N412_2_0 : X_OR2 
      port map ( I0 => N88 , I1 => N407 , O => U382_2_0 ) ;
    U382_N412 : X_OR2 
      port map ( I0 => U382_2_0 , I1 => N406 , O => U382_N412_2_INV ) ;
    U386_N411_2_0 : X_AND2 
      port map ( I0 => N410 , I1 => N409 , O => U386_2_0 ) ;
    U386_N411 : X_AND2 
      port map ( I0 => U386_2_0 , I1 => N88 , O => N411 ) ;
    U391_N420_2_0 : X_OR2 
      port map ( I0 => N88 , I1 => N415 , O => U391_2_0 ) ;
    U391_N420 : X_OR2 
      port map ( I0 => U391_2_0 , I1 => N414 , O => U391_N420_2_INV ) ;
    U395_N419_2_0 : X_AND2 
      port map ( I0 => N418 , I1 => N417 , O => U395_2_0 ) ;
    U395_N419 : X_AND2 
      port map ( I0 => U395_2_0 , I1 => N88 , O => N419 ) ;
    U400_N428_2_0 : X_AND2 
      port map ( I0 => N423 , I1 => N422 , O => U400_2_0 ) ;
    U400_N428 : X_AND2 
      port map ( I0 => U400_2_0 , I1 => N88 , O => N428 ) ;
    U404_N427_2_0 : X_OR2 
      port map ( I0 => N88 , I1 => N426 , O => U404_2_0 ) ;
    U404_N427 : X_OR2 
      port map ( I0 => U404_2_0 , I1 => N425 , O => U404_N427_2_INV ) ;
    U409_N436_2_0 : X_OR2 
      port map ( I0 => N88 , I1 => N431 , O => U409_2_0 ) ;
    U409_N436 : X_OR2 
      port map ( I0 => U409_2_0 , I1 => N430 , O => U409_N436_2_INV ) ;
    U413_N435_2_0 : X_AND2 
      port map ( I0 => N434 , I1 => N433 , O => U413_2_0 ) ;
    U413_N435 : X_AND2 
      port map ( I0 => U413_2_0 , I1 => N88 , O => N435 ) ;
    U417_N440_2_0 : X_OR2 
      port map ( I0 => N87 , I1 => N237 , O => U417_2_0 ) ;
    U417_N440 : X_OR2 
      port map ( I0 => U417_2_0 , I1 => N437 , O => N440 ) ;
    U418_N439_2_0 : X_OR2 
      port map ( I0 => N236 , I1 => N438 , O => U418_2_0 ) ;
    U418_N439 : X_OR2 
      port map ( I0 => U418_2_0 , I1 => N86 , O => N439 ) ;
    U421_N443_2_0 : X_OR2 
      port map ( I0 => N86 , I1 => N235 , O => U421_2_0 ) ;
    U421_N443 : X_OR2 
      port map ( I0 => U421_2_0 , I1 => N87 , O => N443 ) ;
    U422_N442_2_0 : X_AND2 
      port map ( I0 => N441 , I1 => N86 , O => U422_2_0 ) ;
    U422_N442 : X_AND2 
      port map ( I0 => U422_2_0 , I1 => N87 , O => U422_N442_2_INV ) ;
    U426_N448_2_0 : X_OR2 
      port map ( I0 => N446 , I1 => N88 , O => U426_2_0 ) ;
    U426_N448 : X_OR2 
      port map ( I0 => U426_2_0 , I1 => N89 , O => N448 ) ;
    U427_N447_2_0 : X_AND2 
      port map ( I0 => N88 , I1 => N103 , O => U427_2_0 ) ;
    U427_N447 : X_AND2 
      port map ( I0 => U427_2_0 , I1 => N89 , O => U427_N447_2_INV ) ;
    U431_N452_2_0 : X_OR2 
      port map ( I0 => N449 , I1 => N89 , O => U431_2_0 ) ;
    U431_N452 : X_OR2 
      port map ( I0 => U431_2_0 , I1 => N450 , O => N452 ) ;
    U432_N451_2_0 : X_AND2 
      port map ( I0 => N89 , I1 => N105 , O => U432_2_0 ) ;
    U432_N451 : X_AND2 
      port map ( I0 => U432_2_0 , I1 => N450 , O => U432_N451_2_INV ) ;
    U438_N462_2_0 : X_AND2 
      port map ( I0 => N457 , I1 => N456 , O => U438_2_0 ) ;
    U438_N462 : X_AND2 
      port map ( I0 => U438_2_0 , I1 => N88 , O => N462 ) ;
    U442_N461_2_0 : X_OR2 
      port map ( I0 => N88 , I1 => N460 , O => U442_2_0 ) ;
    U442_N461 : X_OR2 
      port map ( I0 => U442_2_0 , I1 => N459 , O => U442_N461_2_INV ) ;
    U447_N470_2_0 : X_AND2 
      port map ( I0 => N465 , I1 => N464 , O => U447_2_0 ) ;
    U447_N470 : X_AND2 
      port map ( I0 => U447_2_0 , I1 => N88 , O => N470 ) ;
    U451_N469_2_0 : X_OR2 
      port map ( I0 => N88 , I1 => N468 , O => U451_2_0 ) ;
    U451_N469 : X_OR2 
      port map ( I0 => U451_2_0 , I1 => N467 , O => U451_N469_2_INV ) ;
    U456_N478_2_0 : X_OR2 
      port map ( I0 => N88 , I1 => N473 , O => U456_2_0 ) ;
    U456_N478 : X_OR2 
      port map ( I0 => U456_2_0 , I1 => N472 , O => U456_N478_2_INV ) ;
    U460_N477_2_0 : X_AND2 
      port map ( I0 => N476 , I1 => N475 , O => U460_2_0 ) ;
    U460_N477 : X_AND2 
      port map ( I0 => U460_2_0 , I1 => N88 , O => N477 ) ;
    U465_N486_2_0 : X_OR2 
      port map ( I0 => N86 , I1 => N481 , O => U465_2_0 ) ;
    U465_N486 : X_OR2 
      port map ( I0 => U465_2_0 , I1 => N480 , O => U465_N486_2_INV ) ;
    U469_N485_2_0 : X_AND2 
      port map ( I0 => N484 , I1 => N483 , O => U469_2_0 ) ;
    U469_N485 : X_AND2 
      port map ( I0 => U469_2_0 , I1 => N86 , O => N485 ) ;
    U474_N494_2_0 : X_AND2 
      port map ( I0 => N489 , I1 => N488 , O => U474_2_0 ) ;
    U474_N494 : X_AND2 
      port map ( I0 => U474_2_0 , I1 => N88 , O => N494 ) ;
    U478_N493_2_0 : X_OR2 
      port map ( I0 => N88 , I1 => N492 , O => U478_2_0 ) ;
    U478_N493 : X_OR2 
      port map ( I0 => U478_2_0 , I1 => N491 , O => U478_N493_2_INV ) ;
    U483_N502_2_0 : X_OR2 
      port map ( I0 => N88 , I1 => N497 , O => U483_2_0 ) ;
    U483_N502 : X_OR2 
      port map ( I0 => U483_2_0 , I1 => N496 , O => U483_N502_2_INV ) ;
    U487_N501_2_0 : X_AND2 
      port map ( I0 => N500 , I1 => N499 , O => U487_2_0 ) ;
    U487_N501 : X_AND2 
      port map ( I0 => U487_2_0 , I1 => N88 , O => N501 ) ;
    U492_N510_2_0 : X_AND2 
      port map ( I0 => N505 , I1 => N504 , O => U492_2_0 ) ;
    U492_N510 : X_AND2 
      port map ( I0 => U492_2_0 , I1 => N88 , O => N510 ) ;
    U496_N509_2_0 : X_OR2 
      port map ( I0 => N88 , I1 => N508 , O => U496_2_0 ) ;
    U496_N509 : X_OR2 
      port map ( I0 => U496_2_0 , I1 => N507 , O => U496_N509_2_INV ) ;
    U501_N518_2_0 : X_OR2 
      port map ( I0 => N88 , I1 => N513 , O => U501_2_0 ) ;
    U501_N518 : X_OR2 
      port map ( I0 => U501_2_0 , I1 => N512 , O => U501_N518_2_INV ) ;
    U505_N517_2_0 : X_AND2 
      port map ( I0 => N516 , I1 => N515 , O => U505_2_0 ) ;
    U505_N517 : X_AND2 
      port map ( I0 => U505_2_0 , I1 => N88 , O => N517 ) ;
    U510_N526_2_0 : X_AND2 
      port map ( I0 => N521 , I1 => N520 , O => U510_2_0 ) ;
    U510_N526 : X_AND2 
      port map ( I0 => U510_2_0 , I1 => N86 , O => N526 ) ;
    U514_N525_2_0 : X_OR2 
      port map ( I0 => N86 , I1 => N524 , O => U514_2_0 ) ;
    U514_N525 : X_OR2 
      port map ( I0 => U514_2_0 , I1 => N523 , O => U514_N525_2_INV ) ;
    U517_N529_2_0 : X_OR2 
      port map ( I0 => N527 , I1 => N88 , O => U517_2_0 ) ;
    U517_N529 : X_OR2 
      port map ( I0 => U517_2_0 , I1 => N89 , O => N529 ) ;
    U518_N528_2_0 : X_AND2 
      port map ( I0 => N88 , I1 => N105 , O => U518_2_0 ) ;
    U518_N528 : X_AND2 
      port map ( I0 => U518_2_0 , I1 => N89 , O => U518_N528_2_INV ) ;