time_sim.vhd

实用的程序代码

    U373 : X_AND2 
      port map ( I0 => N398 , I1 => N399 , O => U373_2_INV ) ;
    U374 : X_INV 
      port map ( I => N238 , O => N400 ) ;
    U377 : X_AND2 
      port map ( I0 => N401 , I1 => N402 , O => U377_2_INV ) ;
    U378 : X_OR2 
      port map ( I0 => N412 , I1 => N411 , O => U378_2_INV ) ;
    U379 : X_INV 
      port map ( I => N89 , O => N405 ) ;
    U380 : X_OR2 
      port map ( I0 => N405 , I1 => N90 , O => U380_2_INV ) ;
    U381 : X_OR2 
      port map ( I0 => N91 , I1 => N89 , O => U381_2_INV ) ;
    U383 : X_INV 
      port map ( I => N104 , O => N408 ) ;
    U384 : X_AND2 
      port map ( I0 => N89 , I1 => N408 , O => U384_2_INV ) ;
    U385 : X_OR2 
      port map ( I0 => N105 , I1 => N89 , O => N409 ) ;
    U387 : X_OR2 
      port map ( I0 => N419 , I1 => N420 , O => U387_2_INV ) ;
    U388 : X_INV 
      port map ( I => N89 , O => N413 ) ;
    U389 : X_OR2 
      port map ( I0 => N413 , I1 => N94 , O => U389_2_INV ) ;
    U390 : X_OR2 
      port map ( I0 => N95 , I1 => N89 , O => U390_2_INV ) ;
    U392 : X_INV 
      port map ( I => N92 , O => N416 ) ;
    U393 : X_AND2 
      port map ( I0 => N89 , I1 => N416 , O => U393_2_INV ) ;
    U394 : X_OR2 
      port map ( I0 => N93 , I1 => N89 , O => N417 ) ;
    U396 : X_OR2 
      port map ( I0 => N428 , I1 => N427 , O => U396_2_INV ) ;
    U397 : X_INV 
      port map ( I => N96 , O => N421 ) ;
    U398 : X_AND2 
      port map ( I0 => N89 , I1 => N421 , O => U398_2_INV ) ;
    U399 : X_OR2 
      port map ( I0 => N97 , I1 => N89 , O => N422 ) ;
    U401 : X_INV 
      port map ( I => N89 , O => N424 ) ;
    U402 : X_OR2 
      port map ( I0 => N424 , I1 => N98 , O => U402_2_INV ) ;
    U403 : X_OR2 
      port map ( I0 => N99 , I1 => N89 , O => U403_2_INV ) ;
    U405 : X_OR2 
      port map ( I0 => N435 , I1 => N436 , O => U405_2_INV ) ;
    U406 : X_INV 
      port map ( I => N89 , O => N429 ) ;
    U407 : X_OR2 
      port map ( I0 => N429 , I1 => N102 , O => U407_2_INV ) ;
    U408 : X_OR2 
      port map ( I0 => N103 , I1 => N89 , O => U408_2_INV ) ;
    U410 : X_INV 
      port map ( I => N100 , O => N432 ) ;
    U411 : X_AND2 
      port map ( I0 => N89 , I1 => N432 , O => U411_2_INV ) ;
    U412 : X_OR2 
      port map ( I0 => N101 , I1 => N89 , O => N433 ) ;
    U414 : X_OR2 
      port map ( I0 => N444 , I1 => N445 , O => N568 ) ;
    U415 : X_INV 
      port map ( I => N87 , O => N438 ) ;
    U416 : X_INV 
      port map ( I => N86 , O => N437 ) ;
    U419 : X_AND2 
      port map ( I0 => N439 , I1 => N440 , O => U419_2_INV ) ;
    U420 : X_INV 
      port map ( I => N234 , O => N441 ) ;
    U423 : X_AND2 
      port map ( I0 => N442 , I1 => N443 , O => U423_2_INV ) ;
    U424 : X_OR2 
      port map ( I0 => N454 , I1 => N453 , O => U424_2_INV ) ;
    U425 : X_INV 
      port map ( I => N90 , O => N446 ) ;
    U428 : X_AND2 
      port map ( I0 => N447 , I1 => N448 , O => U428_2_INV ) ;
    U429 : X_INV 
      port map ( I => N104 , O => N449 ) ;
    U430 : X_INV 
      port map ( I => N88 , O => N450 ) ;
    U433 : X_AND2 
      port map ( I0 => N451 , I1 => N452 , O => U433_2_INV ) ;
    U434 : X_OR2 
      port map ( I0 => N462 , I1 => N461 , O => U434_2_INV ) ;
    U435 : X_INV 
      port map ( I => N91 , O => N455 ) ;
    U436 : X_AND2 
      port map ( I0 => N89 , I1 => N455 , O => U436_2_INV ) ;
    U437 : X_OR2 
      port map ( I0 => N92 , I1 => N89 , O => N456 ) ;
    U439 : X_INV 
      port map ( I => N89 , O => N458 ) ;
    U440 : X_OR2 
      port map ( I0 => N458 , I1 => N93 , O => U440_2_INV ) ;
    U441 : X_OR2 
      port map ( I0 => N94 , I1 => N89 , O => U441_2_INV ) ;
    U443 : X_OR2 
      port map ( I0 => N470 , I1 => N469 , O => U443_2_INV ) ;
    U444 : X_INV 
      port map ( I => N95 , O => N463 ) ;
    U445 : X_AND2 
      port map ( I0 => N89 , I1 => N463 , O => U445_2_INV ) ;
    U446 : X_OR2 
      port map ( I0 => N96 , I1 => N89 , O => N464 ) ;
    U448 : X_INV 
      port map ( I => N89 , O => N466 ) ;
    U449 : X_OR2 
      port map ( I0 => N466 , I1 => N97 , O => U449_2_INV ) ;
    U450 : X_OR2 
      port map ( I0 => N98 , I1 => N89 , O => U450_2_INV ) ;
    U452 : X_OR2 
      port map ( I0 => N477 , I1 => N478 , O => U452_2_INV ) ;
    U453 : X_INV 
      port map ( I => N89 , O => N471 ) ;
    U454 : X_OR2 
      port map ( I0 => N471 , I1 => N101 , O => U454_2_INV ) ;
    U455 : X_OR2 
      port map ( I0 => N102 , I1 => N89 , O => U455_2_INV ) ;
    U457 : X_INV 
      port map ( I => N99 , O => N474 ) ;
    U458 : X_AND2 
      port map ( I0 => N89 , I1 => N474 , O => U458_2_INV ) ;
    U459 : X_OR2 
      port map ( I0 => N100 , I1 => N89 , O => N475 ) ;
    U461 : X_OR2 
      port map ( I0 => N485 , I1 => N486 , O => N567 ) ;
    U462 : X_INV 
      port map ( I => N232 , O => N479 ) ;
    U463 : X_AND2 
      port map ( I0 => N87 , I1 => N233 , O => N480 ) ;
    U464 : X_OR2 
      port map ( I0 => N87 , I1 => N479 , O => U464_2_INV ) ;
    U466 : X_INV 
      port map ( I => N230 , O => N482 ) ;
    U467 : X_AND2 
      port map ( I0 => N87 , I1 => N231 , O => U467_2_INV ) ;
    U468 : X_OR2 
      port map ( I0 => N87 , I1 => N482 , O => N483 ) ;
    U470 : X_OR2 
      port map ( I0 => N494 , I1 => N493 , O => U470_2_INV ) ;
    U471 : X_INV 
      port map ( I => N90 , O => N487 ) ;
    U472 : X_AND2 
      port map ( I0 => N89 , I1 => N487 , O => U472_2_INV ) ;
    U473 : X_OR2 
      port map ( I0 => N91 , I1 => N89 , O => N488 ) ;
    U475 : X_INV 
      port map ( I => N89 , O => N490 ) ;
    U476 : X_OR2 
      port map ( I0 => N490 , I1 => N92 , O => U476_2_INV ) ;
    U477 : X_OR2 
      port map ( I0 => N93 , I1 => N89 , O => U477_2_INV ) ;
    U479 : X_OR2 
      port map ( I0 => N501 , I1 => N502 , O => U479_2_INV ) ;
    U480 : X_INV 
      port map ( I => N89 , O => N495 ) ;
    U481 : X_OR2 
      port map ( I0 => N495 , I1 => N96 , O => U481_2_INV ) ;
    U482 : X_OR2 
      port map ( I0 => N97 , I1 => N89 , O => U482_2_INV ) ;
    U484 : X_INV 
      port map ( I => N94 , O => N498 ) ;
    U485 : X_AND2 
      port map ( I0 => N89 , I1 => N498 , O => U485_2_INV ) ;
    U486 : X_OR2 
      port map ( I0 => N95 , I1 => N89 , O => N499 ) ;
    U488 : X_OR2 
      port map ( I0 => N510 , I1 => N509 , O => U488_2_INV ) ;
    U489 : X_INV 
      port map ( I => N98 , O => N503 ) ;
    U490 : X_AND2 
      port map ( I0 => N89 , I1 => N503 , O => U490_2_INV ) ;
    U491 : X_OR2 
      port map ( I0 => N99 , I1 => N89 , O => N504 ) ;
    U493 : X_INV 
      port map ( I => N89 , O => N506 ) ;
    U494 : X_OR2 
      port map ( I0 => N506 , I1 => N100 , O => U494_2_INV ) ;
    U495 : X_OR2 
      port map ( I0 => N101 , I1 => N89 , O => U495_2_INV ) ;
    U497 : X_OR2 
      port map ( I0 => N517 , I1 => N518 , O => U497_2_INV ) ;
    U498 : X_INV 
      port map ( I => N89 , O => N511 ) ;
    U499 : X_OR2 
      port map ( I0 => N511 , I1 => N104 , O => U499_2_INV ) ;
    U500 : X_OR2 
      port map ( I0 => N105 , I1 => N89 , O => U500_2_INV ) ;
    U502 : X_INV 
      port map ( I => N102 , O => N514 ) ;
    U503 : X_AND2 
      port map ( I0 => N89 , I1 => N514 , O => U503_2_INV ) ;
    U504 : X_OR2 
      port map ( I0 => N103 , I1 => N89 , O => N515 ) ;
    U506 : X_OR2 
      port map ( I0 => N526 , I1 => N525 , O => N566 ) ;
    U507 : X_INV 
      port map ( I => N226 , O => N519 ) ;
    U508 : X_AND2 
      port map ( I0 => N87 , I1 => N227 , O => U508_2_INV ) ;
    U509 : X_OR2 
      port map ( I0 => N87 , I1 => N519 , O => N520 ) ;
    U511 : X_INV 
      port map ( I => N228 , O => N522 ) ;
    U512 : X_AND2 
      port map ( I0 => N87 , I1 => N229 , O => N523 ) ;
    U513 : X_OR2 
      port map ( I0 => N87 , I1 => N522 , O => U513_2_INV ) ;
    U515 : X_OR2 
      port map ( I0 => N534 , I1 => N535 , O => U515_2_INV ) ;
    U516 : X_INV 
      port map ( I => N92 , O => N527 ) ;
    U519 : X_AND2 
      port map ( I0 => N528 , I1 => N529 , O => U519_2_INV ) ;
    U520 : X_INV 
      port map ( I => N90 , O => N530 ) ;
    U521 : X_INV 
      port map ( I => N88 , O => N531 ) ;
    U524 : X_AND2 
      port map ( I0 => N532 , I1 => N533 , O => U524_2_INV ) ;
    U525 : X_OR2 
      port map ( I0 => N542 , I1 => N543 , O => U525_2_INV ) ;
    U526 : X_INV 
      port map ( I => N89 , O => N536 ) ;
    U527 : X_OR2 
      port map ( I0 => N536 , I1 => N95 , O => U527_2_INV ) ;
    U528 : X_OR2 
      port map ( I0 => N96 , I1 => N89 , O => U528_2_INV ) ;
    U530 : X_INV 
      port map ( I => N93 , O => N539 ) ;
    U531 : X_AND2 
      port map ( I0 => N89 , I1 => N539 , O => U531_2_INV ) ;
    U532 : X_OR2 
      port map ( I0 => N94 , I1 => N89 , O => N540 ) ;
    U534 : X_OR2 
      port map ( I0 => N550 , I1 => N551 , O => U534_2_INV ) ;
    U535 : X_INV 
      port map ( I => N89 , O => N544 ) ;
    U536 : X_OR2 
      port map ( I0 => N544 , I1 => N99 , O => U536_2_INV ) ;
    U537 : X_OR2 
      port map ( I0 => N100 , I1 => N89 , O => U537_2_INV ) ;
    U539 : X_INV 
      port map ( I => N97 , O => N547 ) ;
    U540 : X_AND2 
      port map ( I0 => N89 , I1 => N547 , O => U540_2_INV ) ;
    U541 : X_OR2 
      port map ( I0 => N98 , I1 => N89 , O => N548 ) ;
    U543 : X_OR2 
      port map ( I0 => N559 , I1 => N558 , O => U543_2_INV ) ;
    U544 : X_INV 
      port map ( I => N101 , O => N552 ) ;
    U545 : X_AND2 
      port map ( I0 => N89 , I1 => N552 , O => U545_2_INV ) ;
    U546 : X_OR2 
      port map ( I0 => N102 , I1 => N89 , O => N553 ) ;
    U548 : X_INV 
      port map ( I => N89 , O => N555 ) ;
    U549 : X_OR2 
      port map ( I0 => N555 , I1 => N103 , O => U549_2_INV ) ;
    U550 : X_OR2 
      port map ( I0 => N104 , I1 => N89 , O => U550_2_INV ) ;
    U238_1I20 : X_BUF 
      port map ( I => N560 , O => U238_1I20_GTS_TRI ) ;
    U238_1I20_GTS_TRI_0 : X_TRI 
      port map ( I => U238_1I20_GTS_TRI , O => B_P(15) , 
      CTL => U238_1I20_GTS_TRI_2_INV ) ;
    U239_1I20 : X_BUF 
      port map ( I => N561 , O => U239_1I20_GTS_TRI ) ;
    U239_1I20_GTS_TRI_1 : X_TRI 
      port map ( I => U239_1I20_GTS_TRI , O => B_P(14) , 
      CTL => U239_1I20_GTS_TRI_2_INV ) ;
    U240_1I20 : X_BUF 
      port map ( I => N562 , O => U240_1I20_GTS_TRI ) ;
    U240_1I20_GTS_TRI_2 : X_TRI 
      port map ( I => U240_1I20_GTS_TRI , O => B_P(13) , 
      CTL => U240_1I20_GTS_TRI_2_INV ) ;
    U241_1I20 : X_BUF 
      port map ( I => N563 , O => U241_1I20_GTS_TRI ) ;
    U241_1I20_GTS_TRI_3 : X_TRI 
      port map ( I => U241_1I20_GTS_TRI , O => B_P(12) , 
      CTL => U241_1I20_GTS_TRI_2_INV ) ;
    U242_1I20 : X_BUF 
      port map ( I => N564 , O => U242_1I20_GTS_TRI ) ;
    U242_1I20_GTS_TRI_4 : X_TRI 
      port map ( I => U242_1I20_GTS_TRI , O => B_P(11) , 
      CTL => U242_1I20_GTS_TRI_2_INV ) ;
    U243_1I20 : X_BUF 
      port map ( I => N565 , O => U243_1I20_GTS_TRI ) ;
    U243_1I20_GTS_TRI_5 : X_TRI 
      port map ( I => U243_1I20_GTS_TRI , O => B_P(10) , 
      CTL => U243_1I20_GTS_TRI_2_INV ) ;
    U244_1I20 : X_BUF 
      port map ( I => N566 , O => U244_1I20_GTS_TRI ) ;
    U244_1I20_GTS_TRI_6 : X_TRI 
      port map ( I => U244_1I20_GTS_TRI , O => B_P(9) , 
      CTL => U244_1I20_GTS_TRI_2_INV ) ;
    U245_1I20 : X_BUF 
      port map ( I => N567 , O => U245_1I20_GTS_TRI ) ;
    U245_1I20_GTS_TRI_7 : X_TRI 
      port map ( I => U245_1I20_GTS_TRI , O => B_P(8) , 
      CTL => U245_1I20_GTS_TRI_2_INV ) ;
    U246_1I20 : X_BUF 
      port map ( I => N568 , O => U246_1I20_GTS_TRI ) ;
    U246_1I20_GTS_TRI_8 : X_TRI 
      port map ( I => U246_1I20_GTS_TRI , O => B_P(7) , 
      CTL => U246_1I20_GTS_TRI_2_INV ) ;
    U247_1I20 : X_BUF 
      port map ( I => N569 , O => U247_1I20_GTS_TRI ) ;
    U247_1I20_GTS_TRI_9 : X_TRI 
      port map ( I => U247_1I20_GTS_TRI , O => B_P(6) , 
      CTL => U247_1I20_GTS_TRI_2_INV ) ;
    U248_1I20 : X_BUF 
      port map ( I => N570 , O => U248_1I20_GTS_TRI ) ;
    U248_1I20_GTS_TRI_10 : X_TRI 
      port map ( I => U248_1I20_GTS_TRI , O => B_P(5) , 
      CTL => U248_1I20_GTS_TRI_2_INV ) ;
    U249_1I20 : X_BUF 
      port map ( I => N571 , O => U249_1I20_GTS_TRI ) ;
    U249_1I20_GTS_TRI_11 : X_TRI 
      port map ( I => U249_1I20_GTS_TRI , O => B_P(4) ,