time_sim.sdf

实用的程序代码

      (ABSOLUTE
        (PORT I0  (2427:2427:2427) (2427:2427:2427))
        (IOPATH I0 O  (0:0:0) (0:0:0))
        (PORT I1  (4116:4116:4116) (4116:4116:4116))
        (IOPATH I1 O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U276)
    (DELAY
      (ABSOLUTE
        (PORT I  (2515:2515:2515) (2515:2515:2515))
        (IOPATH I O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U278)
    (DELAY
      (ABSOLUTE
        (PORT I0  (2427:2427:2427) (2427:2427:2427))
        (IOPATH I0 O  (0:0:0) (0:0:0))
        (PORT I1  (4126:4126:4126) (4126:4126:4126))
        (IOPATH I1 O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U279)
    (DELAY
      (ABSOLUTE
        (PORT I  (1962:1962:1962) (1962:1962:1962))
        (IOPATH I O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_1_ZCNT_REG_2_Q)
    (DELAY
      (ABSOLUTE
        (PORT I  (0:0:0) (0:0:0))
        (PORT CLK  (1253:1253:1253) (1253:1253:1253))
        (IOPATH CLK O  (2820:2820:2820) (0:0:0))
        (PORT CE  (5039:5039:5039) (5039:5039:5039))
        (IOPATH SET O  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST O  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (RECOVERY (negedge RST) (posedge CLK) (0:0:0))
      (SETUP (posedge CE) (posedge CLK) (0:0:0))
      (SETUP (negedge CE) (posedge CLK) (0:0:0))
      (SETUP (posedge I) (posedge CLK) (0:0:0))
      (SETUP (negedge I) (posedge CLK) (0:0:0))
      (HOLD (posedge CE) (posedge CLK) (0:0:0))
      (HOLD (negedge CE) (posedge CLK) (0:0:0))
      (HOLD (posedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge RST) (posedge CLK) (0:0:0))
      (WIDTH (posedge RST)  (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_1_ZCNT_REG_1_Q)
    (DELAY
      (ABSOLUTE
        (PORT I  (0:0:0) (0:0:0))
        (PORT CLK  (1253:1253:1253) (1253:1253:1253))
        (IOPATH CLK O  (2820:2820:2820) (0:0:0))
        (PORT CE  (5276:5276:5276) (5276:5276:5276))
        (IOPATH SET O  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST O  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (RECOVERY (negedge RST) (posedge CLK) (0:0:0))
      (SETUP (posedge CE) (posedge CLK) (0:0:0))
      (SETUP (negedge CE) (posedge CLK) (0:0:0))
      (SETUP (posedge I) (posedge CLK) (0:0:0))
      (SETUP (negedge I) (posedge CLK) (0:0:0))
      (HOLD (posedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge RST) (posedge CLK) (0:0:0))
      (HOLD (negedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge CE) (posedge CLK) (0:0:0))
      (HOLD (posedge CE) (posedge CLK) (0:0:0))
      (WIDTH (posedge RST)  (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U281)
    (DELAY
      (ABSOLUTE
        (PORT I0  (2427:2427:2427) (2427:2427:2427))
        (IOPATH I0 O  (0:0:0) (0:0:0))
        (PORT I1  (4126:4126:4126) (4126:4126:4126))
        (IOPATH I1 O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U282)
    (DELAY
      (ABSOLUTE
        (PORT I  (1962:1962:1962) (1962:1962:1962))
        (IOPATH I O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U284)
    (DELAY
      (ABSOLUTE
        (PORT I0  (2226:2226:2226) (2226:2226:2226))
        (IOPATH I0 O  (0:0:0) (0:0:0))
        (PORT I1  (2768:2768:2768) (2768:2768:2768))
        (IOPATH I1 O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U285)
    (DELAY
      (ABSOLUTE
        (PORT I  (1650:1650:1650) (1650:1650:1650))
        (IOPATH I O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_1_ZCNT_REG_4_Q)
    (DELAY
      (ABSOLUTE
        (PORT I  (0:0:0) (0:0:0))
        (PORT CLK  (1228:1228:1228) (1228:1228:1228))
        (IOPATH CLK O  (2820:2820:2820) (0:0:0))
        (PORT CE  (4525:4525:4525) (4525:4525:4525))
        (IOPATH SET O  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST O  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (RECOVERY (negedge RST) (posedge CLK) (0:0:0))
      (SETUP (posedge CE) (posedge CLK) (0:0:0))
      (SETUP (negedge CE) (posedge CLK) (0:0:0))
      (SETUP (posedge I) (posedge CLK) (0:0:0))
      (SETUP (negedge I) (posedge CLK) (0:0:0))
      (HOLD (posedge CE) (posedge CLK) (0:0:0))
      (HOLD (negedge CE) (posedge CLK) (0:0:0))
      (HOLD (posedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge RST) (posedge CLK) (0:0:0))
      (WIDTH (posedge RST)  (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_1_ZCNT_REG_3_Q)
    (DELAY
      (ABSOLUTE
        (PORT I  (0:0:0) (0:0:0))
        (PORT CLK  (1253:1253:1253) (1253:1253:1253))
        (IOPATH CLK O  (2820:2820:2820) (0:0:0))
        (PORT CE  (5039:5039:5039) (5039:5039:5039))
        (IOPATH SET O  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST O  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (RECOVERY (negedge RST) (posedge CLK) (0:0:0))
      (SETUP (posedge CE) (posedge CLK) (0:0:0))
      (SETUP (negedge CE) (posedge CLK) (0:0:0))
      (SETUP (posedge I) (posedge CLK) (0:0:0))
      (SETUP (negedge I) (posedge CLK) (0:0:0))
      (HOLD (posedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge RST) (posedge CLK) (0:0:0))
      (HOLD (negedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge CE) (posedge CLK) (0:0:0))
      (HOLD (posedge CE) (posedge CLK) (0:0:0))
      (WIDTH (posedge RST)  (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U287)
    (DELAY
      (ABSOLUTE
        (PORT I0  (2226:2226:2226) (2226:2226:2226))
        (IOPATH I0 O  (0:0:0) (0:0:0))
        (PORT I1  (2768:2768:2768) (2768:2768:2768))
        (IOPATH I1 O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U288)
    (DELAY
      (ABSOLUTE
        (PORT I  (1611:1611:1611) (1611:1611:1611))
        (IOPATH I O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U290)
    (DELAY
      (ABSOLUTE
        (PORT I0  (1902:1902:1902) (1902:1902:1902))
        (IOPATH I0 O  (0:0:0) (0:0:0))
        (PORT I1  (4009:4009:4009) (4009:4009:4009))
        (IOPATH I1 O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U291)
    (DELAY
      (ABSOLUTE
        (PORT I  (1962:1962:1962) (1962:1962:1962))
        (IOPATH I O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_1_ZCNT_REG_6_Q)
    (DELAY
      (ABSOLUTE
        (PORT I  (0:0:0) (0:0:0))
        (PORT CLK  (1253:1253:1253) (1253:1253:1253))
        (IOPATH CLK O  (2820:2820:2820) (0:0:0))
        (PORT CE  (4894:4894:4894) (4894:4894:4894))
        (IOPATH SET O  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST O  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (RECOVERY (negedge RST) (posedge CLK) (0:0:0))
      (SETUP (posedge CE) (posedge CLK) (0:0:0))
      (SETUP (negedge CE) (posedge CLK) (0:0:0))
      (SETUP (posedge I) (posedge CLK) (0:0:0))
      (SETUP (negedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge RST) (posedge CLK) (0:0:0))
      (HOLD (posedge CE) (posedge CLK) (0:0:0))
      (HOLD (negedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge CE) (posedge CLK) (0:0:0))
      (HOLD (posedge I) (posedge CLK) (0:0:0))
      (WIDTH (posedge RST)  (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_1_ZCNT_REG_5_Q)
    (DELAY
      (ABSOLUTE
        (PORT I  (0:0:0) (0:0:0))
        (PORT CLK  (1228:1228:1228) (1228:1228:1228))
        (IOPATH CLK O  (2820:2820:2820) (0:0:0))
        (PORT CE  (4525:4525:4525) (4525:4525:4525))
        (IOPATH SET O  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST O  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (RECOVERY (negedge RST) (posedge CLK) (0:0:0))
      (SETUP (posedge CE) (posedge CLK) (0:0:0))
      (SETUP (negedge CE) (posedge CLK) (0:0:0))
      (SETUP (posedge I) (posedge CLK) (0:0:0))
      (SETUP (negedge I) (posedge CLK) (0:0:0))
      (HOLD (posedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge RST) (posedge CLK) (0:0:0))
      (HOLD (negedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge CE) (posedge CLK) (0:0:0))
      (HOLD (posedge CE) (posedge CLK) (0:0:0))
      (WIDTH (posedge RST)  (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U293)
    (DELAY
      (ABSOLUTE
        (PORT I  (1087:1087:1087) (1087:1087:1087))
        (IOPATH I O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_OR2")
    (INSTANCE U294)
    (DELAY
      (ABSOLUTE
        (PORT I0  (1107:1107:1107) (1107:1107:1107))
        (IOPATH I0 O  (2420:2420:2420) (2420:2420:2420))
        (PORT I1  (0:0:0) (0:0:0))
        (IOPATH I1 O  (2420:2420:2420) (2420:2420:2420))
      )
    )
  )
  (CELL
    (CELLTYPE "X_XOR2")
    (INSTANCE U295)
    (DELAY
      (ABSOLUTE
        (PORT I0  (0:0:0) (0:0:0))
        (IOPATH I0 O  (0:0:0) (0:0:0))
        (PORT I1  (1006:1006:1006) (1006:1006:1006))
        (IOPATH I1 O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U296)
    (DELAY
      (ABSOLUTE
        (PORT I0  (1221:1221:1221) (1221:1221:1221))
        (IOPATH I0 O  (0:0:0) (0:0:0))
        (PORT I1  (1352:1352:1352) (1352:1352:1352))
        (IOPATH I1 O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U297)
    (DELAY
      (ABSOLUTE
        (PORT I0  (0:0:0) (0:0:0))
        (IOPATH I0 O  (2420:2420:2420) (2420:2420:2420))
        (PORT I1  (1470:1470:1470) (1470:1470:1470))
        (IOPATH I1 O  (2420:2420:2420) (2420:2420:2420))
      )
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_1_DCNT_REG_2_Q)
    (DELAY
      (ABSOLUTE
        (PORT I  (0:0:0) (0:0:0))
        (PORT CLK  (1266:1266:1266) (1266:1266:1266))
        (IOPATH CLK O  (2820:2820:2820) (0:0:0))
        (PORT CE  (3927:3927:3927) (3927:3927:3927))
        (IOPATH SET O  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST O  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (RECOVERY (negedge RST) (posedge CLK) (0:0:0))
      (SETUP (posedge CE) (posedge CLK) (0:0:0))
      (SETUP (negedge CE) (posedge CLK) (0:0:0))
      (SETUP (posedge I) (posedge CLK) (0:0:0))
      (SETUP (negedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge CE) (posedge CLK) (0:0:0))
      (HOLD (posedge I) (posedge CLK) (0:0:0))
      (HOLD (posedge CE) (posedge CLK) (0:0:0))
      (HOLD (negedge RST) (posedge CLK) (0:0:0))
      (HOLD (negedge I) (posedge CLK) (0:0:0))
      (WIDTH (posedge RST)  (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_1_DCNT_REG_0_Q)
    (DELAY
      (ABSOLUTE
        (PORT I  (0:0:0) (0:0:0))
        (PORT CLK  (1266:1266:1266) (1266:1266:1266))
        (IOPATH CLK O  (2820:2820:2820) (0:0:0))
        (PORT CE  (4057:4057:4057) (4057:4057:4057))
        (IOPATH SET O  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST O  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (RECOVERY (negedge RST) (posedge CLK) (0:0:0))
      (SETUP (posedge CE) (posedge CLK) (0:0:0))
      (SETUP (negedge CE) (posedge CLK) (0:0:0))
      (SETUP (posedge I) (posedge CLK) (0:0:0))
      (SETUP (negedge I) (posedge CLK) (0:0:0))
      (HOLD (posedge CE) (posedge CLK) (0:0:0))
      (HOLD (negedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge RST) (posedge CLK) (0:0:0))
      (HOLD (posedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge CE) (posedge CLK) (0:0:0))
      (WIDTH (posedge RST)  (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U298)
    (DELAY
      (ABSOLUTE
        (PORT I  (1317:1317:1317) (1317:1317:1317))
        (IOPATH I O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U300)
    (DELAY
      (ABSOLUTE
        (PORT I  (1168:1168:1168) (1168:1168:1168))
        (IOPATH I O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_0_ZCNT_E_REG)
    (DELAY
      (ABSOLUTE
        (PORT I  (820:820:820) (820:820:820))
        (PORT CLK  (1228:1228:1228) (1228:1228:1228))
        (IOPATH CLK O  (2820:2820:2820) (0:0:0))
        (PORT CE  (4025:4025:4025) (4025:4025:4025))
        (IOPATH SET O  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST O  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (RECOVERY (negedge RST) (posedge CLK) (0:0:0))
      (SETUP (posedge CE) (posedge CLK) (0:0:0))
      (SETUP (negedge CE) (posedge CLK) (0:0:0))
      (SETUP (posedge I) (posedge CLK) (0:0:0))
      (SETUP (negedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge I) (posedge CLK) (0:0