📄 time_sim.sdf
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(TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (RECOVERY (negedge RST) (posedge CLK) (0:0:0)) (SETUP (posedge CE) (posedge CLK) (0:0:0)) (SETUP (negedge CE) (posedge CLK) (0:0:0)) (SETUP (posedge I) (posedge CLK) (0:0:0)) (SETUP (negedge I) (posedge CLK) (0:0:0)) (HOLD (posedge CE) (posedge CLK) (0:0:0)) (HOLD (posedge I) (posedge CLK) (0:0:0)) (HOLD (negedge I) (posedge CLK) (0:0:0)) (HOLD (negedge RST) (posedge CLK) (0:0:0)) (HOLD (negedge CE) (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_0_ZCNT_REG_4_Q) (DELAY (ABSOLUTE (PORT I (0:0:0) (0:0:0)) (PORT CLK (1247:1247:1247) (1247:1247:1247)) (IOPATH CLK O (2820:2820:2820) (0:0:0)) (PORT CE (5435:5435:5435) (5435:5435:5435)) (IOPATH SET O (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST O (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (RECOVERY (negedge RST) (posedge CLK) (0:0:0)) (SETUP (posedge CE) (posedge CLK) (0:0:0)) (SETUP (negedge CE) (posedge CLK) (0:0:0)) (SETUP (posedge I) (posedge CLK) (0:0:0)) (SETUP (negedge I) (posedge CLK) (0:0:0)) (HOLD (posedge I) (posedge CLK) (0:0:0)) (HOLD (negedge CE) (posedge CLK) (0:0:0)) (HOLD (negedge I) (posedge CLK) (0:0:0)) (HOLD (posedge CE) (posedge CLK) (0:0:0)) (HOLD (negedge RST) (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U249) (DELAY (ABSOLUTE (PORT I0 (1852:1852:1852) (1852:1852:1852)) (IOPATH I0 O (0:0:0) (0:0:0)) (PORT I1 (4438:4438:4438) (4438:4438:4438)) (IOPATH I1 O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U250) (DELAY (ABSOLUTE (PORT I (3351:3351:3351) (3351:3351:3351)) (IOPATH I O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_0_EQ2_REG) (DELAY (ABSOLUTE (PORT I (820:820:820) (820:820:820)) (PORT CLK (1253:1253:1253) (1253:1253:1253)) (IOPATH CLK O (2820:2820:2820) (0:0:0)) (PORT CE (3886:3886:3886) (3886:3886:3886)) (IOPATH SET O (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST O (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (RECOVERY (negedge RST) (posedge CLK) (0:0:0)) (SETUP (posedge CE) (posedge CLK) (0:0:0)) (SETUP (negedge CE) (posedge CLK) (0:0:0)) (SETUP (posedge I) (posedge CLK) (0:0:0)) (SETUP (negedge I) (posedge CLK) (0:0:0)) (HOLD (negedge I) (posedge CLK) (0:0:0)) (HOLD (negedge CE) (posedge CLK) (0:0:0)) (HOLD (posedge CE) (posedge CLK) (0:0:0)) (HOLD (negedge RST) (posedge CLK) (0:0:0)) (HOLD (posedge I) (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U254) (DELAY (ABSOLUTE (PORT I0 (1413:1413:1413) (1413:1413:1413)) (IOPATH I0 O (0:0:0) (0:0:0)) (PORT I1 (1605:1605:1605) (1605:1605:1605)) (IOPATH I1 O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U255) (DELAY (ABSOLUTE (PORT I (1761:1761:1761) (1761:1761:1761)) (IOPATH I O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_1_EQ2_REG) (DELAY (ABSOLUTE (PORT I (820:820:820) (820:820:820)) (PORT CLK (1235:1235:1235) (1235:1235:1235)) (IOPATH CLK O (2820:2820:2820) (0:0:0)) (PORT CE (3886:3886:3886) (3886:3886:3886)) (IOPATH SET O (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST O (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (RECOVERY (negedge RST) (posedge CLK) (0:0:0)) (SETUP (posedge CE) (posedge CLK) (0:0:0)) (SETUP (negedge CE) (posedge CLK) (0:0:0)) (SETUP (posedge I) (posedge CLK) (0:0:0)) (SETUP (negedge I) (posedge CLK) (0:0:0)) (HOLD (negedge I) (posedge CLK) (0:0:0)) (HOLD (negedge CE) (posedge CLK) (0:0:0)) (HOLD (posedge CE) (posedge CLK) (0:0:0)) (HOLD (negedge RST) (posedge CLK) (0:0:0)) (HOLD (posedge I) (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U257) (DELAY (ABSOLUTE (PORT I0 (1317:1317:1317) (1317:1317:1317)) (IOPATH I0 O (0:0:0) (0:0:0)) (PORT I1 (1010:1010:1010) (1010:1010:1010)) (IOPATH I1 O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U258) (DELAY (ABSOLUTE (PORT I (2276:2276:2276) (2276:2276:2276)) (IOPATH I O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_OR2") (INSTANCE U260) (DELAY (ABSOLUTE (PORT I0 (2065:2065:2065) (2065:2065:2065)) (IOPATH I0 O (0:0:0) (0:0:0)) (PORT I1 (1770:1770:1770) (1770:1770:1770)) (IOPATH I1 O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U262) (DELAY (ABSOLUTE (PORT I (1041:1041:1041) (1041:1041:1041)) (IOPATH I O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_OR2") (INSTANCE U263) (DELAY (ABSOLUTE (PORT I0 (1721:1721:1721) (1721:1721:1721)) (IOPATH I0 O (2420:2420:2420) (2420:2420:2420)) (PORT I1 (0:0:0) (0:0:0)) (IOPATH I1 O (2420:2420:2420) (2420:2420:2420)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U264) (DELAY (ABSOLUTE (PORT I (1169:1169:1169) (1169:1169:1169)) (IOPATH I O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_OR2") (INSTANCE U265) (DELAY (ABSOLUTE (PORT I0 (1721:1721:1721) (1721:1721:1721)) (IOPATH I0 O (2420:2420:2420) (2420:2420:2420)) (PORT I1 (0:0:0) (0:0:0)) (IOPATH I1 O (2420:2420:2420) (2420:2420:2420)) ) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_1_ECNT_REG_1_Q) (DELAY (ABSOLUTE (PORT I (0:0:0) (0:0:0)) (PORT CLK (1266:1266:1266) (1266:1266:1266)) (IOPATH CLK O (2820:2820:2820) (0:0:0)) (PORT CE (4711:4711:4711) (4711:4711:4711)) (IOPATH SET O (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST O (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (RECOVERY (negedge RST) (posedge CLK) (0:0:0)) (SETUP (posedge CE) (posedge CLK) (0:0:0)) (SETUP (negedge CE) (posedge CLK) (0:0:0)) (SETUP (posedge I) (posedge CLK) (0:0:0)) (SETUP (negedge I) (posedge CLK) (0:0:0)) (HOLD (posedge CE) (posedge CLK) (0:0:0)) (HOLD (negedge I) (posedge CLK) (0:0:0)) (HOLD (negedge CE) (posedge CLK) (0:0:0)) (HOLD (negedge RST) (posedge CLK) (0:0:0)) (HOLD (posedge I) (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_1_ECNT_REG_0_Q) (DELAY (ABSOLUTE (PORT I (0:0:0) (0:0:0)) (PORT CLK (1266:1266:1266) (1266:1266:1266)) (IOPATH CLK O (2820:2820:2820) (0:0:0)) (PORT CE (4711:4711:4711) (4711:4711:4711)) (IOPATH SET O (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST O (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (RECOVERY (negedge RST) (posedge CLK) (0:0:0)) (SETUP (posedge CE) (posedge CLK) (0:0:0)) (SETUP (negedge CE) (posedge CLK) (0:0:0)) (SETUP (posedge I) (posedge CLK) (0:0:0)) (SETUP (negedge I) (posedge CLK) (0:0:0)) (HOLD (negedge CE) (posedge CLK) (0:0:0)) (HOLD (posedge I) (posedge CLK) (0:0:0)) (HOLD (negedge RST) (posedge CLK) (0:0:0)) (HOLD (posedge CE) (posedge CLK) (0:0:0)) (HOLD (negedge I) (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U266) (DELAY (ABSOLUTE (PORT I (1316:1316:1316) (1316:1316:1316)) (IOPATH I O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_OR2") (INSTANCE U267) (DELAY (ABSOLUTE (PORT I0 (1230:1230:1230) (1230:1230:1230)) (IOPATH I0 O (2420:2420:2420) (2420:2420:2420)) (PORT I1 (0:0:0) (0:0:0)) (IOPATH I1 O (2420:2420:2420) (2420:2420:2420)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U268) (DELAY (ABSOLUTE (PORT I (1169:1169:1169) (1169:1169:1169)) (IOPATH I O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_OR2") (INSTANCE U269) (DELAY (ABSOLUTE (PORT I0 (1230:1230:1230) (1230:1230:1230)) (IOPATH I0 O (2420:2420:2420) (2420:2420:2420)) (PORT I1 (0:0:0) (0:0:0)) (IOPATH I1 O (2420:2420:2420) (2420:2420:2420)) ) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_1_ECNT_REG_3_Q) (DELAY (ABSOLUTE (PORT I (0:0:0) (0:0:0)) (PORT CLK (1266:1266:1266) (1266:1266:1266)) (IOPATH CLK O (2820:2820:2820) (0:0:0)) (PORT CE (4323:4323:4323) (4323:4323:4323)) (IOPATH SET O (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST O (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (RECOVERY (negedge RST) (posedge CLK) (0:0:0)) (SETUP (posedge CE) (posedge CLK) (0:0:0)) (SETUP (negedge CE) (posedge CLK) (0:0:0)) (SETUP (posedge I) (posedge CLK) (0:0:0)) (SETUP (negedge I) (posedge CLK) (0:0:0)) (HOLD (posedge CE) (posedge CLK) (0:0:0)) (HOLD (negedge I) (posedge CLK) (0:0:0)) (HOLD (negedge CE) (posedge CLK) (0:0:0)) (HOLD (negedge RST) (posedge CLK) (0:0:0)) (HOLD (posedge I) (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_1_ECNT_REG_2_Q) (DELAY (ABSOLUTE (PORT I (0:0:0) (0:0:0)) (PORT CLK (1266:1266:1266) (1266:1266:1266)) (IOPATH CLK O (2820:2820:2820) (0:0:0)) (PORT CE (4323:4323:4323) (4323:4323:4323)) (IOPATH SET O (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST O (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (RECOVERY (negedge RST) (posedge CLK) (0:0:0)) (SETUP (posedge CE) (posedge CLK) (0:0:0)) (SETUP (negedge CE) (posedge CLK) (0:0:0)) (SETUP (posedge I) (posedge CLK) (0:0:0)) (SETUP (negedge I) (posedge CLK) (0:0:0)) (HOLD (negedge CE) (posedge CLK) (0:0:0)) (HOLD (posedge I) (posedge CLK) (0:0:0)) (HOLD (negedge RST) (posedge CLK) (0:0:0)) (HOLD (posedge CE) (posedge CLK) (0:0:0)) (HOLD (negedge I) (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U270) (DELAY (ABSOLUTE (PORT I (1025:1025:1025) (1025:1025:1025)) (IOPATH I O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_OR2") (INSTANCE U271) (DELAY (ABSOLUTE (PORT I0 (1492:1492:1492) (1492:1492:1492)) (IOPATH I0 O (2420:2420:2420) (2420:2420:2420)) (PORT I1 (0:0:0) (0:0:0)) (IOPATH I1 O (2420:2420:2420) (2420:2420:2420)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U272) (DELAY (ABSOLUTE (PORT I0 (2427:2427:2427) (2427:2427:2427)) (IOPATH I0 O (0:0:0) (0:0:0)) (PORT I1 (4116:4116:4116) (4116:4116:4116)) (IOPATH I1 O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U273) (DELAY (ABSOLUTE (PORT I (2396:2396:2396) (2396:2396:2396)) (IOPATH I O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_1_ZCNT_REG_0_Q) (DELAY (ABSOLUTE (PORT I (0:0:0) (0:0:0)) (PORT CLK (1253:1253:1253) (1253:1253:1253)) (IOPATH CLK O (2820:2820:2820) (0:0:0)) (PORT CE (5276:5276:5276) (5276:5276:5276)) (IOPATH SET O (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST O (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (RECOVERY (negedge RST) (posedge CLK) (0:0:0)) (SETUP (posedge CE) (posedge CLK) (0:0:0)) (SETUP (negedge CE) (posedge CLK) (0:0:0)) (SETUP (posedge I) (posedge CLK) (0:0:0)) (SETUP (negedge I) (posedge CLK) (0:0:0)) (HOLD (posedge CE) (posedge CLK) (0:0:0)) (HOLD (negedge CE) (posedge CLK) (0:0:0)) (HOLD (posedge I) (posedge CLK) (0:0:0)) (HOLD (negedge I) (posedge CLK) (0:0:0)) (HOLD (negedge RST) (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U275) (DELAY
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