time_sim.vhd

实用的程序代码

  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_0_CY4_MUXA_OUT_2_INV , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_0_CY4_C2_AND_1_INV , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_0_CY4_MUXC_AND_1_INV , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_0_CY4_C6_OR_0_INV , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_0_CY4_G4_AND_1_INV , 
  I_1_LT_113_LT_LT_U8_S0_SUB_AND3_CO_5_0_INV , 
  I_1_LT_113_LT_LT_U8_S0_SUB_AND1_CO_5_1_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_AND3_A_1_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_AND3_A_2_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_AND3_B_0_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_AND3_B_2_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_C1_AND_1_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_MUXA_OUT_2_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_C2_AND_1_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_MUXC_AND_1_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_C6_OR_0_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_G4_AND_1_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_1_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_2_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_0_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_2_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_C1_AND_1_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_2_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_C2_AND_1_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND_1_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_C6_OR_0_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_G4_AND_1_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_3_CY4_AND3_A_1_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_3_CY4_AND3_A_2_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_3_CY4_AND3_B_0_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_3_CY4_AND3_B_2_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_3_CY4_C1_AND_1_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_3_CY4_MUXA_OUT_2_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_3_CY4_C2_AND_1_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_3_CY4_MUXC_AND_1_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_3_CY4_C6_OR_0_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_3_CY4_G4_AND_1_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_2_CY4_AND3_A_1_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_2_CY4_AND3_A_2_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_2_CY4_AND3_B_0_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_2_CY4_AND3_B_2_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_2_CY4_C1_AND_1_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_2_CY4_MUXA_OUT_2_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_2_CY4_C2_AND_1_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_2_CY4_MUXC_AND_1_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_2_CY4_C6_OR_0_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_2_CY4_G4_AND_1_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_1_CY4_AND3_A_1_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_1_CY4_AND3_A_2_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_1_CY4_AND3_B_0_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_1_CY4_AND3_B_2_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_1_CY4_C1_AND_1_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_1_CY4_MUXA_OUT_2_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_1_CY4_C2_AND_1_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_1_CY4_MUXC_AND_1_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_1_CY4_C6_OR_0_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_1_CY4_G4_AND_1_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_0_CY4_AND3_A_1_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_0_CY4_AND3_A_2_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_0_CY4_AND3_B_0_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_0_CY4_AND3_B_2_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_0_CY4_C1_AND_1_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_0_CY4_MUXA_OUT_2_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_0_CY4_C2_AND_1_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_0_CY4_MUXC_AND_1_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_0_CY4_C6_OR_0_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_CY4_0_CY4_G4_AND_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_AND3_A_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_AND3_A_2_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_AND3_B_2_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_C1_AND_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_MUXA_OUT_2_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_C2_AND_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_MUXC_AND_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_C6_OR_0_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_G4_AND_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_4_CY4_AND3_A_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_4_CY4_AND3_A_2_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_4_CY4_AND3_B_2_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_4_CY4_C1_AND_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_4_CY4_MUXA_OUT_2_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_4_CY4_C2_AND_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_4_CY4_MUXC_AND_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_4_CY4_C6_OR_0_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_4_CY4_G4_AND_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_3_CY4_AND3_A_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_3_CY4_AND3_A_2_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_3_CY4_AND3_B_2_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_3_CY4_C1_AND_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_3_CY4_MUXA_OUT_2_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_3_CY4_C2_AND_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_3_CY4_MUXC_AND_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_3_CY4_C6_OR_0_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_3_CY4_G4_AND_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_2_CY4_AND3_A_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_2_CY4_AND3_A_2_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_2_CY4_AND3_B_2_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_2_CY4_C1_AND_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_2_CY4_MUXA_OUT_2_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_2_CY4_C2_AND_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_2_CY4_MUXC_AND_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_2_CY4_C6_OR_0_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_2_CY4_G4_AND_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_1_CY4_AND3_A_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_1_CY4_AND3_A_2_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_1_CY4_AND3_B_2_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_1_CY4_C1_AND_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_1_CY4_MUXA_OUT_2_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_1_CY4_C2_AND_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_1_CY4_MUXC_AND_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_1_CY4_C6_OR_0_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_1_CY4_G4_AND_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_0_CY4_AND3_A_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_0_CY4_AND3_A_2_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_0_CY4_AND3_B_2_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_0_CY4_C1_AND_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_0_CY4_MUXA_OUT_2_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_0_CY4_C2_AND_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_0_CY4_MUXC_AND_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_0_CY4_C6_OR_0_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_CY4_0_CY4_G4_AND_1_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_AND3_CO_5_0_INV , 
  I_0_LT_113_LT_LT_U8_S0_SUB_AND1_CO_5_1_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_3_CY4_AND3_A_1_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_3_CY4_AND3_A_2_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_3_CY4_AND3_B_0_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_3_CY4_AND3_B_2_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_3_CY4_C1_AND_1_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_3_CY4_MUXA_OUT_2_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_3_CY4_C2_AND_1_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_3_CY4_MUXC_AND_1_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_3_CY4_C6_OR_0_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_3_CY4_G4_AND_1_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_2_CY4_AND3_A_1_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_2_CY4_AND3_A_2_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_2_CY4_AND3_B_0_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_2_CY4_AND3_B_2_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_2_CY4_C1_AND_1_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_2_CY4_MUXA_OUT_2_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_2_CY4_C2_AND_1_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_2_CY4_MUXC_AND_1_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_2_CY4_C6_OR_0_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_2_CY4_G4_AND_1_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_1_CY4_AND3_A_1_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_1_CY4_AND3_A_2_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_1_CY4_AND3_B_0_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_1_CY4_AND3_B_2_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_1_CY4_C1_AND_1_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_1_CY4_MUXA_OUT_2_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_1_CY4_C2_AND_1_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_1_CY4_MUXC_AND_1_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_1_CY4_C6_OR_0_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_1_CY4_G4_AND_1_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_0_CY4_AND3_A_1_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_0_CY4_AND3_A_2_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_0_CY4_AND3_B_0_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_0_CY4_AND3_B_2_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_0_CY4_C1_AND_1_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_0_CY4_MUXA_OUT_2_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_0_CY4_C2_AND_1_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_0_CY4_MUXC_AND_1_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_0_CY4_C6_OR_0_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_CY4_0_CY4_G4_AND_1_INV , U180_2_INV , U181_2_INV , 
  U184_2_INV , U193_2_INV , U198_2_INV , U199_2_INV , U202_2_INV , U211_2_INV , 
  U215_2_INV , U217_2_INV , U219_2_INV , U221_2_INV , U223_2_INV , U227_2_INV , 
  U231_2_INV , U234_2_INV , U237_2_INV , U240_2_INV , U243_2_INV , U246_2_INV , 
  U249_2_INV , U254_2_INV , U257_2_INV , U263_2_INV , U265_2_INV , U267_2_INV , 
  U269_2_INV , U271_2_INV , U272_2_INV , U275_2_INV , U278_2_INV , U281_2_INV , 
  U284_2_INV , U287_2_INV , U290_2_INV , U294_2_INV , U309_2_INV , U310_2_INV , 
  U314_2_INV , U315_2_INV , U323_2_INV , U324_2_INV , U332_2_INV , U333_2_INV , 
  U336_2_INV , U342_2_INV , U346_2_INV , U350_2_INV , U353_2_INV , U359_2_INV , 
  U363_2_INV , U367_2_INV , 
  I_0_ADD_106_PLUS_U6_S0_1_XOR4_F_SUM_2_I_0_N991_4_2_0_0_INV , 
  I_0_ADD_106_PLUS_U6_S0_1_XOR3_G_SUM_1_I_0_RETURN989_3_2_0_0_INV , 
  I_0_ADD_106_PLUS_U6_S0_1_XOR2_F_SUM_1_I_0_RETURN989_2_2_0_0_INV , 
  I_0_ADD_106_PLUS_U6_S0_1_XOR1_G_SUM_0_I_0_RETURN989_1_2_0_0_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_XOR4_F_SUM_2_I_1_N991_4_2_0_0_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_XOR3_G_SUM_1_I_1_RETURN989_3_2_0_0_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_XOR2_F_SUM_1_I_1_RETURN989_2_2_0_0_INV , 
  I_1_ADD_106_PLUS_U6_S0_1_XOR1_G_SUM_0_I_1_RETURN989_1_2_0_0_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_XOR6_F_SUM_3_I_1_RETURN1110_6_2_0_0_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_XOR5_G_SUM_2_I_1_RETURN1110_5_2_0_0_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_XOR4_F_SUM_2_I_1_RETURN1110_4_2_0_0_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_XOR3_G_SUM_1_I_1_RETURN1110_3_2_0_0_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_XOR2_F_SUM_1_I_1_RETURN1110_2_2_0_0_INV , 
  I_1_ADD_117_PLUS_U8_S0_1_XOR1_G_SUM_0_I_1_RETURN1110_1_2_0_0_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_XOR6_F_SUM_3_I_0_RETURN1110_6_2_0_0_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_XOR5_G_SUM_2_I_0_RETURN1110_5_2_0_0_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_XOR4_F_SUM_2_I_0_RETURN1110_4_2_0_0_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_XOR3_G_SUM_1_I_0_RETURN1110_3_2_0_0_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_XOR2_F_SUM_1_I_0_RETURN1110_2_2_0_0_INV , 
  I_0_ADD_117_PLUS_U8_S0_1_XOR1_G_SUM_0_I_0_RETURN1110_1_2_0_0_INV , 
  U156_N111_2_INV , U157_N107_2_INV , U160_N98_2_INV , U163_N97_2_INV , 
  U166_N93_2_INV , U169_N92_2_INV , U174_N94_2_INV , U176_N95_2_INV , 
  U187_N151_2_INV , U192_N155_2_INV , U205_N163_2_INV , U210_N167_2_INV , 
  U252_I_0_EQ2282_2_INV , U253_I_1_EQ2282_2_INV , U299_N118_2_INV , 
  U301_N84_2_INV , U303_N119_2_INV , U305_N81_2_INV , U320_N263_2_INV , 
  U329_N270_2_INV , U349_N283_2_INV , U366_N296_2_INV , U151_1I20_GTS_TRI_2_INV 
  , U152_1I20_GTS_TRI_2_INV , GND , GSR , VCC , GTS : STD_LOGIC ;
  signal I_0_ECNT : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal I_0_N991 : STD_LOGIC_VECTOR ( 4 downto 4 );
  signal I_0_RETURN989 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal I_1_ZCNT : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal I_1_ECNT : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal I_1_N991 : STD_LOGIC_VECTOR ( 4 downto 4 );
  signal I_1_RETURN989 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal I_1_RETURN1110 : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal I_0_ZCNT : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal I_0_RETURN1110 : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal I_0_ZCNT465 : STD_LOGIC_VECTOR ( 6 downto 6 );
  signal I_0_N328 : STD_LOGIC_VECTOR ( 0 downto 0 );
  signal I_1_ECNT462 : STD_LOGIC_VECTOR ( 4 downto 4 );
  signal I_1_N319 : STD_LOGIC_VECTOR ( 0 downto 0 );
  signal I_0_N265 : STD_LOGIC_VECTOR ( 0 downto 0 );
  signal I_1_N265 : STD_LOGIC_VECTOR ( 0 downto 0 );
  signal I_0_N319 : STD_LOGIC_VECTOR ( 0 downto 0 );
  signal I_0_DCNT : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal I_1_N328 : STD_LOGIC_VECTOR ( 0 downto 0 );
  signal I_1_DCNT : STD_LOGIC_VECTOR ( 2 downto 0 );
  begin
    U144 : X_BUF 
      port map ( I => A_CHECK , O => N14 ) ;
    U145 : X_BUF 
      port map ( I => B_CHECK , O => N15 ) ;
    U146 : X_BUF 
      port map ( I => RESET , O => N16 ) ;
    U148 : X_BUF 
      port map ( I => CLKEN , O => N18 ) ;
    U149 : X_BUF 
      port map ( I => A_TICK , O => N19 ) ;
    U150 : X_BUF 
      port map ( I => B_TICK , O => N20 ) ;
    U153 : X_INV 
      port map ( I => N16 , O => I_0_N1163 ) ;
    U154 : X_INV 
      port map ( I => N297 , O => I_0_ST_INT446 ) ;
    U155 : X_INV 
      port map ( I => N298 , O => I_1_ST_INT446 ) ;
    I_