time_sim.vhd

实用的程序代码

-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 16:38:45 1998
-- Design file: time_sim.nga
-- Device: 4005epc84-2
----- CELL ROC -----
-- Model for  Reset-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity ROC is
    generic ( InstancePath: STRING := "*";
              WIDTH : Time := 0 ns) ;
    port( O : out std_ulogic := '1' ) ;
    attribute VITAL_LEVEL0 of ROC : entity is TRUE ;
end ROC ;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      if (WIDTH <= 0 ns) then
         assert FALSE report
         "*** Error: a positive value of WIDTH must be specified ***"
         severity failure;
      else
         wait for WIDTH;
         O <= '0' ;
      end if;
      wait;
    end process ONE_SHOT ;
end ROC_V ;

configuration CFG_ROC_V of ROC is
    for ROC_V
    end for ;
end CFG_ROC_V ;
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity GATE_REDUCE is
  port (
    A_CHECK : in STD_LOGIC := 'X' ;
    B_CHECK : in STD_LOGIC := 'X' ;
    RESET : in STD_LOGIC := 'X' ;
    CLOCK : in STD_LOGIC := 'X' ;
    CLKEN : in STD_LOGIC := 'X' ;
    A_TICK : in STD_LOGIC := 'X' ;
    B_TICK : in STD_LOGIC := 'X' ;
    ST_A : out STD_LOGIC ;
    ST_B : out STD_LOGIC 
  ) ;
end GATE_REDUCE ;

architecture STRUCTURE of GATE_REDUCE is
  component ROC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal N123 , I_1_LT_113_LT_LT_GRND_SIG , I_0_LOGIC1_Q , I_0_LOGIC0_Q , 
  I_1_RETURN1051 , N122 , N121 , I_0_LT_113_LT_LT_GRND_SIG , I_0_RETURN1051 , 
  N120 , N14 , N15 , N16 , N17 , N18 , N19 , N20 , N297 , N298 , I_0_N1163 , 
  I_0_ST_INT446 , I_1_ST_INT446 , N111 , N107 , I_0_N292 , N135 , N136 , N98 , 
  N119 , N105 , N137 , N138 , N81 , N97 , I_1_EQ2 , I_0_ECNT_E , I_0_ECNT_E434 
  , I_0_N256 , N139 , N140 , N93 , N118 , N109 , N141 , N142 , N84 , N92 , 
  I_0_EQ2 , N115 , N104 , I_1_N292 , N108 , N143 , N94 , I_1_E2RQ , I_1_ECNT_E 
  , I_1_ECNT_E434 , I_1_N256 , N144 , N95 , I_0_E2RQ , N117 , N145 , N146 , 
  N147 , I_0_E2RQ562 , N148 , N149 , I_0_N274 , I_0_CLREVENT273 , I_0_N247 , 
  N152 , N151 , N150 , I_0_N283 , I_0_EQ2282 , N153 , I_0_N301 , N154 , N155 , 
  I_0_N310 , I_0_CLRZERO309 , N156 , N157 , N158 , N159 , I_1_E2RQ562 , N160 , 
  N161 , I_1_N274 , I_1_CLREVENT273 , I_1_N247 , N164 , N163 , N162 , I_1_N283 
  , I_1_EQ2282 , N165 , I_1_N301 , N166 , N167 , I_1_N310 , I_1_CLRZERO309 , 
  N168 , N169 , N172 , I_0_CLREVENT , N170 , N171 , N173 , N176 , N174 , N175 , 
  N177 , N179 , N178 , N180 , N184 , N182 , N181 , N183 , N186 , N185 , 
  I_0_CLRZERO , N190 , N188 , N187 , N189 , N192 , N191 , N196 , N194 , N193 , 
  N195 , N198 , N197 , N202 , N200 , N199 , N201 , N204 , N203 , N206 , N205 , 
  N208 , N207 , N209 , N210 , N213 , I_1_CLREVENT , N211 , N212 , N214 , N217 , 
  N215 , N216 , N218 , N220 , N219 , I_1_CLRZERO , N221 , N223 , N222 , N227 , 
  N225 , N224 , N226 , N229 , N228 , N233 , N231 , N230 , N232 , N235 , N234 , 
  N239 , N237 , N236 , N238 , N240 , N244 , N242 , N241 , N243 , N245 , N246 , 
  I_0_ZCNT_E , N247 , N248 , I_1_ZCNT_E , N249 , N252 , N251 , N250 , N253 , 
  N256 , N255 , N254 , N257 , N263 , N258 , N259 , N260 , N261 , N262 , N264 , 
  N270 , N265 , N266 , N267 , N268 , N269 , N273 , N272 , N271 , N278 , N275 , 
  N274 , N277 , N276 , N279 , N280 , N283 , N281 , N282 , N286 , N285 , N284 , 
  N291 , N288 , N287 , N290 , N289 , N292 , N293 , N296 , N294 , N295 , 
  I_0_ST_INT_REG_GSR_OR , I_0_ECNT_E_REG_GSR_OR , I_0_ZCNT_REG_6_GSR_OR , 
  I_1_ST_INT_REG_GSR_OR , I_1_ECNT_E_REG_GSR_OR , I_1_ECNT_REG_4_GSR_OR , 
  I_0_E2RQ_REG_GSR_OR , I_1_E2RQ_REG_GSR_OR , I_0_ECNT_REG_1_GSR_OR , 
  I_0_ECNT_REG_0_GSR_OR , I_0_ECNT_REG_3_GSR_OR , I_0_ECNT_REG_2_GSR_OR , 
  I_0_ECNT_REG_4_GSR_OR , I_0_DCNT_REG_2_GSR_OR , I_0_DCNT_REG_0_GSR_OR , 
  I_0_ZCNT_REG_1_GSR_OR , I_0_ZCNT_REG_0_GSR_OR , I_0_ZCNT_REG_3_GSR_OR , 
  I_0_ZCNT_REG_2_GSR_OR , I_0_ZCNT_REG_5_GSR_OR , I_0_ZCNT_REG_4_GSR_OR , 
  I_0_EQ2_REG_GSR_OR , I_1_EQ2_REG_GSR_OR , I_1_ECNT_REG_1_GSR_OR , 
  I_1_ECNT_REG_0_GSR_OR , I_1_ECNT_REG_3_GSR_OR , I_1_ECNT_REG_2_GSR_OR , 
  I_1_ZCNT_REG_0_GSR_OR , I_1_ZCNT_REG_2_GSR_OR , I_1_ZCNT_REG_1_GSR_OR , 
  I_1_ZCNT_REG_4_GSR_OR , I_1_ZCNT_REG_3_GSR_OR , I_1_ZCNT_REG_6_GSR_OR , 
  I_1_ZCNT_REG_5_GSR_OR , I_1_DCNT_REG_2_GSR_OR , I_1_DCNT_REG_0_GSR_OR , 
  I_0_ZCNT_E_REG_GSR_OR , I_1_ZCNT_E_REG_GSR_OR , I_0_DCNT_REG_1_GSR_OR , 
  I_1_DCNT_REG_1_GSR_OR , I_0_CLRZERO_REG_GSR_OR , I_1_CLRZERO_REG_GSR_OR , 
  I_0_CLREVENT_REG_GSR_OR , I_1_CLREVENT_REG_GSR_OR , 
  I_0_ADD_106_PLUS_U6_S0_1_CO_5 , I_0_ADD_106_PLUS_U6_S0_1_CO_4 , 
  I_0_ADD_106_PLUS_U6_S0_1_CO_3 , I_0_ADD_106_PLUS_U6_S0_1_CO_2 , 
  I_0_ADD_106_PLUS_U6_S0_1_CO_1 , I_0_ADD_106_PLUS_U6_S0_1_CY4_2_C0 , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_C1 , I_0_ADD_106_PLUS_U6_S0_1_CY4_2_C2 , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_C3 , I_0_ADD_106_PLUS_U6_S0_1_CY4_2_C4 , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_C5 , I_0_ADD_106_PLUS_U6_S0_1_CY4_2_C6 , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_C7 , I_0_ADD_106_PLUS_U6_S0_1_CY4_2_COUT , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_AND3_A , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_AND3_B , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_AND3_C , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_MUXC_OUT , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_C1_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_C0_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_MUXA_OUT , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_F2_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_F2_XOR , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_F1_XOR , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_C2_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_C3_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_MUXB_OUT , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_CIN_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_MUXC_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_G1_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_G1_XOR , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_G4_XOR , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_C6_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_C6_OR , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_COUT0_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_G4_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_31_ONE , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_2_CY4_31_ZERO , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_C0 , I_0_ADD_106_PLUS_U6_S0_1_CY4_1_C1 , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_C2 , I_0_ADD_106_PLUS_U6_S0_1_CY4_1_C3 , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_C4 , I_0_ADD_106_PLUS_U6_S0_1_CY4_1_C5 , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_C6 , I_0_ADD_106_PLUS_U6_S0_1_CY4_1_C7 , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_AND3_A , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_AND3_B , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_AND3_C , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_MUXC_OUT , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_C1_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_C0_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_F2_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_F2_XOR , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_F1_XOR , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_C2_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_C3_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_CIN_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_G1_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_G1_XOR , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_G4_XOR , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_C6_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_C6_OR , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_COUT0_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_G4_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_C0 , I_0_ADD_106_PLUS_U6_S0_1_CY4_0_C1 , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_C2 , I_0_ADD_106_PLUS_U6_S0_1_CY4_0_C3 , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_C4 , I_0_ADD_106_PLUS_U6_S0_1_CY4_0_C5 , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_C6 , I_0_ADD_106_PLUS_U6_S0_1_CY4_0_C7 , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_AND3_A , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_AND3_B , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_AND3_C , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_MUXC_OUT , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_C1_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_C0_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_F2_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_F2_XOR , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_F1_XOR , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_C2_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_C3_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_MUXB_OUT , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_CIN_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_G1_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_G1_XOR , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_G4_XOR , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_C6_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_C6_OR , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_COUT0_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_G4_AND , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_33_ONE , 
  I_0_ADD_106_PLUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
  I_0_ADD_106_PLUS_U6_S0_1_XOR4_F_SUM_2_2_0 , 
  I_0_ADD_106_PLUS_U6_S0_1_XOR3_G_SUM_1_2_0 , 
  I_0_ADD_106_PLUS_U6_S0_1_XOR2_F_SUM_1_2_0 , 
  I_0_ADD_106_PLUS_U6_S0_1_XOR1_G_SUM_0_2_0 , I_1_LT_113_LT_LT_U8_S0_OVFL , 
  I_1_LT_113_LT_LT_U8_S0_SUB_OR1_CO_5 , I_1_LT_113_LT_LT_U8_S0_SUB_AND3_CO_5 , 
  I_1_LT_113_LT_LT_U8_S0_SUB_AND1_CO_5 , I_1_LT_113_LT_LT_U8_S0_SUB_AND2_CO_5 , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CO_SIG , I_1_LT_113_LT_LT_U8_S0_SUB_CO_6 , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CO_4 , I_1_LT_113_LT_LT_U8_S0_SUB_CO_2 , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CO_0 , I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_C0 , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_C1 , I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_C2 , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_C3 , I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_C4 , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_C5 , I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_C6 , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_C7 , I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_COUT0 
  , I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_COUT , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_AND3_A , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_AND3_B , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_AND3_C , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_MUXC_OUT , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_C1_AND , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_C0_AND , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_MUXA_OUT , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_F2_AND , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_F2_XOR , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_F1_XOR , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_C2_AND , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_C3_AND , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_MUXB_OUT , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_CIN_AND , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_MUXC_AND , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_G1_AND , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_G1_XOR , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_G4_XOR , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_C6_AND , 
  I_1_LT_113_LT_LT_U8_S0_SUB_CY4_5_CY4_C6_OR ,