time_sim.sdf

实用的程序代码

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "GATE_REDUCE")
  (DATE "Tue Jan  6 16:43:16 1998")
  (VENDOR "Xilinx")
  (PROGRAM "Xilinx VHDL SDF writer")
  (VERSION "M1.4.12")
  (DIVIDER /)
  (VOLTAGE 5.00:5.00:5.00)
  (PROCESS "best=1.0:nom=1.0:worst=1.0")
  (TEMPERATURE 25.00:25.00:25.00)
  (TIMESCALE 1ps)
  (CELL
    (CELLTYPE "X_BUF")
    (INSTANCE U156)
    (DELAY
      (ABSOLUTE
        (PORT I  (0:0:0) (0:0:0))
        (IOPATH I O  (2050:2050:2050) (2050:2050:2050))
      )
    )
  )
  (CELL
    (CELLTYPE "X_BUF")
    (INSTANCE U157)
    (DELAY
      (ABSOLUTE
        (PORT I  (0:0:0) (0:0:0))
        (IOPATH I O  (2050:2050:2050) (2050:2050:2050))
      )
    )
  )
  (CELL
    (CELLTYPE "X_BUF")
    (INSTANCE U158)
    (DELAY
      (ABSOLUTE
        (PORT I  (0:0:0) (0:0:0))
        (IOPATH I O  (2050:2050:2050) (2050:2050:2050))
      )
    )
  )
  (CELL
    (CELLTYPE "X_BUF")
    (INSTANCE U160)
    (DELAY
      (ABSOLUTE
        (PORT I  (0:0:0) (0:0:0))
        (IOPATH I O  (2050:2050:2050) (2050:2050:2050))
      )
    )
  )
  (CELL
    (CELLTYPE "X_BUF")
    (INSTANCE U161)
    (DELAY
      (ABSOLUTE
        (PORT I  (0:0:0) (0:0:0))
        (IOPATH I O  (2050:2050:2050) (2050:2050:2050))
      )
    )
  )
  (CELL
    (CELLTYPE "X_BUF")
    (INSTANCE U162)
    (DELAY
      (ABSOLUTE
        (PORT I  (0:0:0) (0:0:0))
        (IOPATH I O  (2050:2050:2050) (2050:2050:2050))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U165)
    (DELAY
      (ABSOLUTE
        (PORT I  (1888:1888:1888) (1888:1888:1888))
        (IOPATH I O  (1600:1600:1600) (1600:1600:1600))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U166)
    (DELAY
      (ABSOLUTE
        (PORT I  (1031:1031:1031) (1031:1031:1031))
        (IOPATH I O  (2420:2420:2420) (2420:2420:2420))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U167)
    (DELAY
      (ABSOLUTE
        (PORT I  (1132:1132:1132) (1132:1132:1132))
        (IOPATH I O  (2420:2420:2420) (2420:2420:2420))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U168)
    (DELAY
      (ABSOLUTE
        (PORT I  (0:0:0) (0:0:0))
        (IOPATH I O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U169)
    (DELAY
      (ABSOLUTE
        (PORT I  (2674:2674:2674) (2674:2674:2674))
        (IOPATH I O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_OR2")
    (INSTANCE U171)
    (DELAY
      (ABSOLUTE
        (PORT I0  (1173:1173:1173) (1173:1173:1173))
        (IOPATH I0 O  (1600:1600:1600) (1600:1600:1600))
        (PORT I1  (0:0:0) (0:0:0))
        (IOPATH I1 O  (1600:1600:1600) (1600:1600:1600))
      )
    )
  )
  (CELL
    (CELLTYPE "X_OR2")
    (INSTANCE U172)
    (DELAY
      (ABSOLUTE
        (PORT I0  (1163:1163:1163) (1163:1163:1163))
        (IOPATH I0 O  (0:0:0) (0:0:0))
        (PORT I1  (4439:4439:4439) (4439:4439:4439))
        (IOPATH I1 O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_0_CLRZERO_REG)
    (DELAY
      (ABSOLUTE
        (PORT I  (820:820:820) (820:820:820))
        (PORT CLK  (1247:1247:1247) (1247:1247:1247))
        (IOPATH CLK O  (2820:2820:2820) (0:0:0))
        (PORT CE  (4681:4681:4681) (4681:4681:4681))
        (IOPATH SET O  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST O  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (RECOVERY (negedge RST) (posedge CLK) (0:0:0))
      (SETUP (posedge CE) (posedge CLK) (0:0:0))
      (SETUP (negedge CE) (posedge CLK) (0:0:0))
      (SETUP (posedge I) (posedge CLK) (0:0:0))
      (SETUP (negedge I) (posedge CLK) (0:0:0))
      (HOLD (posedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge RST) (posedge CLK) (0:0:0))
      (HOLD (negedge CE) (posedge CLK) (0:0:0))
      (HOLD (posedge CE) (posedge CLK) (0:0:0))
      (HOLD (negedge I) (posedge CLK) (0:0:0))
      (WIDTH (posedge RST)  (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U174)
    (DELAY
      (ABSOLUTE
        (PORT I  (1348:1348:1348) (1348:1348:1348))
        (IOPATH I O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U176)
    (DELAY
      (ABSOLUTE
        (PORT I0  (0:0:0) (0:0:0))
        (IOPATH I0 O  (1600:1600:1600) (1600:1600:1600))
        (PORT I1  (1603:1603:1603) (1603:1603:1603))
        (IOPATH I1 O  (1600:1600:1600) (1600:1600:1600))
      )
    )
  )
  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U178)
    (DELAY
      (ABSOLUTE
        (PORT I0  (0:0:0) (0:0:0))
        (IOPATH I0 O  (1600:1600:1600) (1600:1600:1600))
        (PORT I1  (1426:1426:1426) (1426:1426:1426))
        (IOPATH I1 O  (1600:1600:1600) (1600:1600:1600))
      )
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_0_EQ2_REG)
    (DELAY
      (ABSOLUTE
        (PORT I  (820:820:820) (820:820:820))
        (PORT CLK  (1235:1235:1235) (1235:1235:1235))
        (IOPATH CLK O  (2820:2820:2820) (0:0:0))
        (PORT CE  (4543:4543:4543) (4543:4543:4543))
        (IOPATH SET O  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST O  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (RECOVERY (negedge RST) (posedge CLK) (0:0:0))
      (SETUP (posedge CE) (posedge CLK) (0:0:0))
      (SETUP (negedge CE) (posedge CLK) (0:0:0))
      (SETUP (posedge I) (posedge CLK) (0:0:0))
      (SETUP (negedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge RST) (posedge CLK) (0:0:0))
      (HOLD (posedge CE) (posedge CLK) (0:0:0))
      (HOLD (negedge CE) (posedge CLK) (0:0:0))
      (HOLD (posedge I) (posedge CLK) (0:0:0))
      (WIDTH (posedge RST)  (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U179)
    (DELAY
      (ABSOLUTE
        (PORT I  (0:0:0) (0:0:0))
        (IOPATH I O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U180)
    (DELAY
      (ABSOLUTE
        (PORT I  (1566:1566:1566) (1566:1566:1566))
        (IOPATH I O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_OR2")
    (INSTANCE U182)
    (DELAY
      (ABSOLUTE
        (PORT I0  (2066:2066:2066) (2066:2066:2066))
        (IOPATH I0 O  (1600:1600:1600) (1600:1600:1600))
        (PORT I1  (0:0:0) (0:0:0))
        (IOPATH I1 O  (1600:1600:1600) (1600:1600:1600))
      )
    )
  )
  (CELL
    (CELLTYPE "X_OR2")
    (INSTANCE U183)
    (DELAY
      (ABSOLUTE
        (PORT I0  (1389:1389:1389) (1389:1389:1389))
        (IOPATH I0 O  (0:0:0) (0:0:0))
        (PORT I1  (1744:1744:1744) (1744:1744:1744))
        (IOPATH I1 O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_0_ST_INT_REG)
    (DELAY
      (ABSOLUTE
        (PORT I  (0:0:0) (0:0:0))
        (PORT CLK  (1241:1241:1241) (1241:1241:1241))
        (IOPATH CLK O  (2820:2820:2820) (0:0:0))
        (PORT CE  (4316:4316:4316) (4316:4316:4316))
        (IOPATH SET O  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST O  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (RECOVERY (negedge RST) (posedge CLK) (0:0:0))
      (SETUP (posedge CE) (posedge CLK) (0:0:0))
      (SETUP (negedge CE) (posedge CLK) (0:0:0))
      (SETUP (posedge I) (posedge CLK) (0:0:0))
      (SETUP (negedge I) (posedge CLK) (0:0:0))
      (HOLD (posedge CE) (posedge CLK) (0:0:0))
      (HOLD (negedge RST) (posedge CLK) (0:0:0))
      (HOLD (negedge CE) (posedge CLK) (0:0:0))
      (HOLD (posedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge I) (posedge CLK) (0:0:0))
      (WIDTH (posedge RST)  (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_0_ECNT_E_REG)
    (DELAY
      (ABSOLUTE
        (PORT I  (820:820:820) (820:820:820))
        (PORT CLK  (1235:1235:1235) (1235:1235:1235))
        (IOPATH CLK O  (2820:2820:2820) (0:0:0))
        (PORT CE  (3907:3907:3907) (3907:3907:3907))
        (IOPATH SET O  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST O  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (RECOVERY (negedge RST) (posedge CLK) (0:0:0))
      (SETUP (posedge CE) (posedge CLK) (0:0:0))
      (SETUP (negedge CE) (posedge CLK) (0:0:0))
      (SETUP (posedge I) (posedge CLK) (0:0:0))
      (SETUP (negedge I) (posedge CLK) (0:0:0))
      (HOLD (posedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge CE) (posedge CLK) (0:0:0))
      (HOLD (negedge RST) (posedge CLK) (0:0:0))
      (HOLD (posedge CE) (posedge CLK) (0:0:0))
      (WIDTH (posedge RST)  (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U187)
    (DELAY
      (ABSOLUTE
        (PORT I  (1813:1813:1813) (1813:1813:1813))
        (IOPATH I O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U188)
    (DELAY
      (ABSOLUTE
        (PORT I  (2217:2217:2217) (2217:2217:2217))
        (IOPATH I O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U190)
    (DELAY
      (ABSOLUTE
        (PORT I  (1718:1718:1718) (1718:1718:1718))
        (IOPATH I O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U191)
    (DELAY
      (ABSOLUTE
        (PORT I  (1402:1402:1402) (1402:1402:1402))
        (IOPATH I O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_0_ECNT_REG_0_Q)
    (DELAY
      (ABSOLUTE
        (PORT I  (0:0:0) (0:0:0))
        (PORT CLK  (1228:1228:1228) (1228:1228:1228))
        (IOPATH CLK O  (2820:2820:2820) (0:0:0))
        (PORT CE  (4185:4185:4185) (4185:4185:4185))
        (IOPATH SET O  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST O  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (RECOVERY (negedge RST) (posedge CLK) (0:0:0))
      (SETUP (posedge CE) (posedge CLK) (0:0:0))
      (SETUP (negedge CE) (posedge CLK) (0:0:0))
      (SETUP (posedge I) (posedge CLK) (0:0:0))
      (SETUP (negedge I) (posedge CLK) (0:0:0))
      (HOLD (posedge CE) (posedge CLK) (0:0:0))
      (HOLD (negedge RST) (posedge CLK) (0:0:0))
      (HOLD (negedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge CE) (posedge CLK) (0:0:0))
      (HOLD (posedge I) (posedge CLK) (0:0:0))
      (WIDTH (posedge RST)  (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U193)
    (DELAY
      (ABSOLUTE
        (PORT I  (1906:1906:1906) (1906:1906:1906))
        (IOPATH I O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_1_ST_INT_REG)
    (DELAY
      (ABSOLUTE
        (PORT I  (0:0:0) (0:0:0))
        (PORT CLK  (1247:1247:1247) (1247:1247:1247))
        (IOPATH CLK O  (2820:2820:2820) (0:0:0))
        (PORT CE  (4867:4867:4867) (4867:4867:4867))
        (IOPATH SET O  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST O  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (RECOVERY (negedge RST) (posedge CLK) (0:0:0))
      (SETUP (posedge CE) (posedge CLK) (0:0:0))
      (SETUP (negedge CE) (posedge CLK) (0:0:0))
      (SETUP (posedge I) (posedge CLK) (0:0:0))
      (SETUP (negedge I) (posedge CLK) (0:0:0))
      (HOLD (posedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge RST) (posedge CLK) (0:0:0))
      (HOLD (negedge CE) (posedge CLK) (0:0:0))
      (HOLD (negedge I) (posedge CLK) (0:0:0))
      (HOLD (posedge CE) (posedge CLK) (0:0:0))
      (WIDTH (posedge RST)  (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U196)
    (DELAY
      (ABSOLUTE
        (PORT I  (1775:1775:1775) (1775:1775:1775))
        (IOPATH I O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_1_ECNT_E_REG)
    (DELAY
      (ABSOLUTE
        (PORT I  (820:820:820) (820:820:820))
        (PORT CLK  (1266:1266:1266) (1266:1266:1266))
        (IOPATH CLK O  (2820:2820:2820) (0:0:0))
        (PORT CE  (3799:3799:3799) (3799:3799:3799))
        (IOPATH SET O  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST O  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))