time_sim.vhd

实用的程序代码

      port map ( I0 => U262_2_0 , I1 => N336 , O => U262_N223_2_INV ) ;
    U264_N224_2_0 : X_OR2 
      port map ( I0 => I_1_ZCNT(3) , I1 => I_1_LT_114_LT_LT_AEQB(2) , 
      O => U264_2_0 ) ;
    U264_N224 : X_OR2 
      port map ( I0 => U264_2_0 , I1 => I_1_ZCNT(4) , O => N224 ) ;
    U271_I_1_N292_2_0 : X_AND2 
      port map ( I0 => N18 , I1 => N228 , O => U271_2_0 ) ;
    U271_I_1_N292 : X_AND2 
      port map ( I0 => U271_2_0 , I1 => N20 , O => I_1_N292 ) ;
    U283_I_0_EQ2282_2_0 : X_OR2 
      port map ( I0 => I_0_ECNT(4) , I1 => I_0_ECNT(3) , O => U283_2_0 ) ;
    U283_I_0_EQ2282_2_1 : X_OR2 
      port map ( I0 => I_0_ECNT(2) , I1 => N104 , O => U283_2_1 ) ;
    U283_I_0_EQ2282 : X_OR2 
      port map ( I0 => U283_2_0 , I1 => U283_2_1 , O => U283_I_0_EQ2282_2_INV 
      ) ;
    U284_I_1_EQ2282_2_0 : X_OR2 
      port map ( I0 => I_1_ECNT(4) , I1 => I_1_ECNT(3) , O => U284_2_0 ) ;
    U284_I_1_EQ2282_2_1 : X_OR2 
      port map ( I0 => I_1_ECNT(2) , I1 => N103 , O => U284_2_1 ) ;
    U284_I_1_EQ2282 : X_OR2 
      port map ( I0 => U284_2_0 , I1 => U284_2_1 , O => U284_I_1_EQ2282_2_INV 
      ) ;
    U287_I_1_N247_2_0 : X_AND2 
      port map ( I0 => N242 , I1 => N241 , O => U287_2_0 ) ;
    U287_I_1_N247 : X_AND2 
      port map ( I0 => U287_2_0 , I1 => N18 , O => I_1_N247 ) ;
    U290_I_0_N247_2_0 : X_AND2 
      port map ( I0 => N244 , I1 => N243 , O => U290_2_0 ) ;
    U290_I_0_N247 : X_AND2 
      port map ( I0 => U290_2_0 , I1 => N18 , O => I_0_N247 ) ;
    U292_I_0_N292_2_0 : X_AND2 
      port map ( I0 => N19 , I1 => N245 , O => U292_2_0 ) ;
    U292_I_0_N292 : X_AND2 
      port map ( I0 => U292_2_0 , I1 => N18 , O => I_0_N292 ) ;
    U309_N139_2_0 : X_AND2 
      port map ( I0 => I_0_DCNT(1) , I1 => I_0_DCNT(0) , O => U309_2_0 ) ;
    U309_N139 : X_AND2 
      port map ( I0 => U309_2_0 , I1 => N261 , O => U309_N139_2_INV ) ;
    U311_N89_2_0 : X_OR2 
      port map ( I0 => N262 , I1 => I_0_DCNT(1) , O => U311_2_0 ) ;
    U311_N89 : X_OR2 
      port map ( I0 => U311_2_0 , I1 => I_0_DCNT(0) , O => U311_N89_2_INV ) ;
    U313_N140_2_0 : X_AND2 
      port map ( I0 => I_1_DCNT(1) , I1 => I_1_DCNT(0) , O => U313_2_0 ) ;
    U313_N140 : X_AND2 
      port map ( I0 => U313_2_0 , I1 => N263 , O => U313_N140_2_INV ) ;
    U315_N86_2_0 : X_OR2 
      port map ( I0 => N264 , I1 => I_1_DCNT(1) , O => U315_2_0 ) ;
    U315_N86 : X_OR2 
      port map ( I0 => U315_2_0 , I1 => I_1_DCNT(0) , O => U315_N86_2_INV ) ;
    U319_N110_2_0 : X_AND2 
      port map ( I0 => I_0_ECNT(1) , I1 => I_0_ECNT(0) , O => U319_2_0 ) ;
    U319_N110 : X_AND2 
      port map ( I0 => U319_2_0 , I1 => I_0_ECNT(2) , O => N110 ) ;
    U322_N270_2_0 : X_OR2 
      port map ( I0 => N89 , I1 => I_0_EQ2 , O => U322_2_0 ) ;
    U322_N270 : X_OR2 
      port map ( I0 => U322_2_0 , I1 => N335 , O => N270 ) ;
    U327_N106_2_0 : X_AND2 
      port map ( I0 => I_0_ZCNT(1) , I1 => I_0_ZCNT(0) , O => U327_2_0 ) ;
    U327_N106 : X_AND2 
      port map ( I0 => U327_2_0 , I1 => I_0_LT_114_LT_LT_AEQB(2) , O => N106 ) ;
    U330_N105_2_0 : X_AND2 
      port map ( I0 => I_0_ZCNT(3) , I1 => N106 , O => U330_2_0 ) ;
    U330_N105 : X_AND2 
      port map ( I0 => U330_2_0 , I1 => I_0_ZCNT(4) , O => N105 ) ;
    U334_N100_2_0 : X_AND2 
      port map ( I0 => I_1_ECNT(1) , I1 => I_1_ECNT(0) , O => U334_2_0 ) ;
    U334_N100 : X_AND2 
      port map ( I0 => U334_2_0 , I1 => I_1_ECNT(2) , O => N100 ) ;
    U337_N99_2_0 : X_AND2 
      port map ( I0 => I_1_ZCNT(1) , I1 => I_1_ZCNT(0) , O => U337_2_0 ) ;
    U337_N99 : X_AND2 
      port map ( I0 => U337_2_0 , I1 => I_1_LT_114_LT_LT_AEQB(2) , O => N99 ) ;
    U340_N98_2_0 : X_AND2 
      port map ( I0 => I_1_ZCNT(3) , I1 => N99 , O => U340_2_0 ) ;
    U340_N98 : X_AND2 
      port map ( I0 => U340_2_0 , I1 => I_1_ZCNT(4) , O => N98 ) ;
    U343_N285_2_0 : X_OR2 
      port map ( I0 => N86 , I1 => I_1_EQ2 , O => U343_2_0 ) ;
    U343_N285 : X_OR2 
      port map ( I0 => U343_2_0 , I1 => N336 , O => N285 ) ;
    U352_N295_2_0 : X_OR2 
      port map ( I0 => N291 , I1 => N290 , O => U352_2_0 ) ;
    U352_N295_2_1 : X_OR2 
      port map ( I0 => N120 , I1 => N14 , O => U352_2_1 ) ;
    U352_N295 : X_OR2 
      port map ( I0 => U352_2_0 , I1 => U352_2_1 , O => U352_N295_2_INV ) ;
    U363_N304_2_0 : X_OR2 
      port map ( I0 => N300 , I1 => N299 , O => U363_2_0 ) ;
    U363_N304_2_1 : X_OR2 
      port map ( I0 => N116 , I1 => N15 , O => U363_2_1 ) ;
    U363_N304 : X_OR2 
      port map ( I0 => U363_2_0 , I1 => U363_2_1 , O => U363_N304_2_INV ) ;
    U374_N311_2_0 : X_OR2 
      port map ( I0 => N308 , I1 => I_0_EQ2 , O => U374_2_0 ) ;
    U374_N311 : X_OR2 
      port map ( I0 => U374_2_0 , I1 => N335 , O => N311 ) ;
    U383_N317_2_0 : X_AND2 
      port map ( I0 => N18 , I1 => N316 , O => U383_2_0 ) ;
    U383_N317 : X_AND2 
      port map ( I0 => U383_2_0 , I1 => N14 , O => U383_N317_2_INV ) ;
    U386_N120_2_0 : X_AND2 
      port map ( I0 => N119 , I1 => N318 , O => U386_2_0 ) ;
    U386_N120 : X_AND2 
      port map ( I0 => U386_2_0 , I1 => I_0_LT_114_LT_LT_AEQB(2) , O => N120 ) ;
    U387_N319_2_0 : X_OR2 
      port map ( I0 => I_0_ZCNT(4) , I1 => I_0_ZCNT(3) , O => U387_2_0 ) ;
    U387_N319_2_1 : X_OR2 
      port map ( I0 => I_0_ZCNT(1) , I1 => I_0_ZCNT(0) , O => U387_2_1 ) ;
    U387_N319 : X_OR2 
      port map ( I0 => U387_2_0 , I1 => U387_2_1 , O => N319 ) ;
    U395_N326_2_0 : X_OR2 
      port map ( I0 => N323 , I1 => I_1_EQ2 , O => U395_2_0 ) ;
    U395_N326 : X_OR2 
      port map ( I0 => U395_2_0 , I1 => N336 , O => N326 ) ;
    U404_N332_2_0 : X_AND2 
      port map ( I0 => N18 , I1 => N331 , O => U404_2_0 ) ;
    U404_N332 : X_AND2 
      port map ( I0 => U404_2_0 , I1 => N15 , O => U404_N332_2_INV ) ;
    U407_N116_2_0 : X_AND2 
      port map ( I0 => N115 , I1 => N333 , O => U407_2_0 ) ;
    U407_N116 : X_AND2 
      port map ( I0 => U407_2_0 , I1 => I_1_LT_114_LT_LT_AEQB(2) , O => N116 ) ;
    U408_N334_2_0 : X_OR2 
      port map ( I0 => I_1_ZCNT(4) , I1 => I_1_ZCNT(3) , O => U408_2_0 ) ;
    U408_N334_2_1 : X_OR2 
      port map ( I0 => I_1_ZCNT(1) , I1 => I_1_ZCNT(0) , O => U408_2_1 ) ;
    U408_N334 : X_OR2 
      port map ( I0 => U408_2_0 , I1 => U408_2_1 , O => N334 ) ;
    U176_2_INV_46 : X_INV 
      port map ( I => U176_2_INV , O => I_0_N310 ) ;
    U201_2_INV_47 : X_INV 
      port map ( I => U201_2_INV , O => N175 ) ;
    U203_2_INV_48 : X_INV 
      port map ( I => U203_2_INV , O => N171 ) ;
    U204_2_INV_49 : X_INV 
      port map ( I => U204_2_INV , O => N172 ) ;
    U205_2_INV_50 : X_INV 
      port map ( I => U205_2_INV , O => N174 ) ;
    U206_2_INV_51 : X_INV 
      port map ( I => U206_2_INV , O => I_0_ECNT462(0) ) ;
    U213_2_INV_52 : X_INV 
      port map ( I => U213_2_INV , O => N181 ) ;
    U218_2_INV_53 : X_INV 
      port map ( I => U218_2_INV , O => N186 ) ;
    U219_2_INV_54 : X_INV 
      port map ( I => U219_2_INV , O => I_0_CLRZERO309 ) ;
    U222_2_INV_55 : X_INV 
      port map ( I => U222_2_INV , O => N190 ) ;
    U224_2_INV_56 : X_INV 
      port map ( I => U224_2_INV , O => N191 ) ;
    U225_2_INV_57 : X_INV 
      port map ( I => U225_2_INV , O => N192 ) ;
    U226_2_INV_58 : X_INV 
      port map ( I => U226_2_INV , O => N195 ) ;
    U227_2_INV_59 : X_INV 
      port map ( I => U227_2_INV , O => N194 ) ;
    U234_2_INV_60 : X_INV 
      port map ( I => U234_2_INV , O => N202 ) ;
    U245_2_INV_61 : X_INV 
      port map ( I => U245_2_INV , O => N210 ) ;
    U246_2_INV_62 : X_INV 
      port map ( I => U246_2_INV , O => I_1_CLRZERO309 ) ;
    U249_2_INV_63 : X_INV 
      port map ( I => U249_2_INV , O => N213 ) ;
    U250_2_INV_64 : X_INV 
      port map ( I => U250_2_INV , O => I_0_E2RQ562 ) ;
    U253_2_INV_65 : X_INV 
      port map ( I => U253_2_INV , O => I_0_N274 ) ;
    U256_2_INV_66 : X_INV 
      port map ( I => U256_2_INV , O => N218 ) ;
    U257_2_INV_67 : X_INV 
      port map ( I => U257_2_INV , O => I_1_E2RQ562 ) ;
    U260_2_INV_68 : X_INV 
      port map ( I => U260_2_INV , O => I_1_N274 ) ;
    U263_2_INV_69 : X_INV 
      port map ( I => U263_2_INV , O => I_1_N310 ) ;
    U267_2_INV_70 : X_INV 
      port map ( I => U267_2_INV , O => N225 ) ;
    U268_2_INV_71 : X_INV 
      port map ( I => U268_2_INV , O => N226 ) ;
    U269_2_INV_72 : X_INV 
      port map ( I => U269_2_INV , O => N229 ) ;
    U273_2_INV_73 : X_INV 
      port map ( I => U273_2_INV , O => N234 ) ;
    U285_2_INV_74 : X_INV 
      port map ( I => U285_2_INV , O => N242 ) ;
    U288_2_INV_75 : X_INV 
      port map ( I => U288_2_INV , O => N244 ) ;
    U294_2_INV_76 : X_INV 
      port map ( I => U294_2_INV , O => N246 ) ;
    U295_2_INV_77 : X_INV 
      port map ( I => U295_2_INV , O => N247 ) ;
    U296_2_INV_78 : X_INV 
      port map ( I => U296_2_INV , O => N249 ) ;
    U304_2_INV_79 : X_INV 
      port map ( I => U304_2_INV , O => N260 ) ;
    U318_2_INV_80 : X_INV 
      port map ( I => U318_2_INV , O => N267 ) ;
    U323_2_INV_81 : X_INV 
      port map ( I => U323_2_INV , O => N269 ) ;
    U324_2_INV_82 : X_INV 
      port map ( I => U324_2_INV , O => I_0_ECNT_E434 ) ;
    U333_2_INV_83 : X_INV 
      port map ( I => U333_2_INV , O => N278 ) ;
    U344_2_INV_84 : X_INV 
      port map ( I => U344_2_INV , O => N284 ) ;
    U345_2_INV_85 : X_INV 
      port map ( I => U345_2_INV , O => I_1_ECNT_E434 ) ;
    U348_2_INV_86 : X_INV 
      port map ( I => U348_2_INV , O => N288 ) ;
    U355_2_INV_87 : X_INV 
      port map ( I => U355_2_INV , O => N293 ) ;
    U356_2_INV_88 : X_INV 
      port map ( I => U356_2_INV , O => N96 ) ;
    U359_2_INV_89 : X_INV 
      port map ( I => U359_2_INV , O => N297 ) ;
    U366_2_INV_90 : X_INV 
      port map ( I => U366_2_INV , O => N302 ) ;
    U367_2_INV_91 : X_INV 
      port map ( I => U367_2_INV , O => N93 ) ;
    U370_2_INV_92 : X_INV 
      port map ( I => U370_2_INV , O => N306 ) ;
    U376_2_INV_93 : X_INV 
      port map ( I => U376_2_INV , O => N312 ) ;
    U380_2_INV_94 : X_INV 
      port map ( I => U380_2_INV , O => I_0_N319(0) ) ;
    U384_2_INV_95 : X_INV 
      port map ( I => U384_2_INV , O => I_0_CLREVENT273 ) ;
    U391_2_INV_96 : X_INV 
      port map ( I => U391_2_INV , O => N321 ) ;
    U397_2_INV_97 : X_INV 
      port map ( I => U397_2_INV , O => N327 ) ;
    U401_2_INV_98 : X_INV 
      port map ( I => U401_2_INV , O => I_1_N319(0) ) ;
    U405_2_INV_99 : X_INV 
      port map ( I => U405_2_INV , O => I_1_CLREVENT273 ) ;
    U170_N153_2_INV_100 : X_INV 
      port map ( I => U170_N153_2_INV , O => N153 ) ;
    U175_N157_2_INV_101 : X_INV 
      port map ( I => U175_N157_2_INV , O => N157 ) ;
    U181_N160_2_INV_102 : X_INV 
      port map ( I => U181_N160_2_INV , O => N160 ) ;
    U185_N122_2_INV_103 : X_INV 
      port map ( I => U185_N122_2_INV , O => N122 ) ;
    U186_N118_2_INV_104 : X_INV 
      port map ( I => U186_N118_2_INV , O => N118 ) ;
    U189_N102_2_INV_105 : X_INV 
      port map ( I => U189_N102_2_INV , O => N102 ) ;
    U192_N101_2_INV_106 : X_INV 
      port map ( I => U192_N101_2_INV , O => N101 ) ;
    U194_N103_2_INV_107 : X_INV 
      port map ( I => U194_N103_2_INV , O => N103 ) ;
    U197_N104_2_INV_108 : X_INV 
      port map ( I => U197_N104_2_INV , O => N104 ) ;
    U214_N182_2_INV_109 : X_INV 
      port map ( I => U214_N182_2_INV , O => N182 ) ;
    U235_N205_2_INV_110 : X_INV 
      port map ( I => U235_N205_2_INV , O => N205 ) ;
    U238_N109_2_INV_111 : X_INV 
      port map ( I => U238_N109_2_INV , O => N109 ) ;
    U241_N108_2_INV_112 : X_INV 
      port map ( I => U241_N108_2_INV , O => N108 ) ;
    U262_N223_2_INV_113 : X_INV 
      port map ( I => U262_N223_2_INV , O => N223 ) ;
    U283_I_0_EQ2282_2_INV_114 : X_INV 
      port map ( I => U283_I_0_EQ2282_2_INV , O => I_0_EQ2282 ) ;
    U284_I_1_EQ2282_2_INV_115 : X_INV 
      port map ( I => U284_I_1_EQ2282_2_INV , O => I_1_EQ2282 ) ;
    U309_N139_2_INV_116 : X_INV 
      port map ( I => U309_N139_2_INV , O => N139 ) ;
    U311_N89_2_INV_117 : X_INV 
      port map ( I => U311_N89_2_INV , O => N89 ) ;
    U313_N140_2_INV_118 : X_INV 
      port map ( I => U313_N140_2_INV , O => N140 ) ;
    U315_N86_2_INV_119 : X_INV 
      port map ( I => U315_N86_2_INV , O => N86 ) ;
    U352_N295_2_INV_120 : X_INV 
      port map ( I => U352_N295_2_INV , O => N295 ) ;
    U363_N304_2_INV_121 : X_INV 
      port map ( I => U363_N304_2_INV , O => N304 ) ;
    U383_N317_2_INV_122 : X_INV 
      port map ( I => U383_N317_2_INV , O => N317 ) ;
    U404_N332_2_INV_123 : X_INV 
      port map ( I => U404_N332_2_INV , O => N332 ) ;
    U163_1I20_GTS_TRI_2_INV_124 : X_INV 
      port map ( I => GTS , O => U163_1I20_GTS_TRI_2_INV ) ;
    U164_1I20_GTS_TRI_2_INV_125 : X_INV 
      port map ( I => GTS , O => U164_1I20_GTS_TRI_2_INV ) ;
    GND_126 : X_ZERO 
      port map ( O => GND ) ;
    ROC_NGD2VHDL : ROC 
      port map ( O => GSR ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;