time_sim.vhd

实用的程序代码

    U351 : X_INV 
      port map ( I => I_0_ZCNT_E , O => N291 ) ;
    U353 : X_INV 
      port map ( I => N293 , O => N294 ) ;
    U354 : X_INV 
      port map ( I => N94 , O => N292 ) ;
    U355 : X_AND2 
      port map ( I0 => N292 , I1 => N14 , O => U355_2_INV ) ;
    U356 : X_OR2 
      port map ( I0 => N294 , I1 => I_0_CLRZERO , O => U356_2_INV ) ;
    U357 : X_INV 
      port map ( I => N297 , O => N298 ) ;
    U358 : X_INV 
      port map ( I => N93 , O => N296 ) ;
    U359 : X_AND2 
      port map ( I0 => N296 , I1 => N18 , O => U359_2_INV ) ;
    U360 : X_OR2 
      port map ( I0 => N304 , I1 => N298 , O => I_1_N328(0) ) ;
    U361 : X_INV 
      port map ( I => N18 , O => N299 ) ;
    U362 : X_INV 
      port map ( I => I_1_ZCNT_E , O => N300 ) ;
    U364 : X_INV 
      port map ( I => N302 , O => N303 ) ;
    U365 : X_INV 
      port map ( I => N91 , O => N301 ) ;
    U366 : X_AND2 
      port map ( I0 => N301 , I1 => N15 , O => U366_2_INV ) ;
    U367 : X_OR2 
      port map ( I0 => N303 , I1 => I_1_CLRZERO , O => U367_2_INV ) ;
    U368 : X_INV 
      port map ( I => N306 , O => N307 ) ;
    U369 : X_INV 
      port map ( I => N312 , O => N305 ) ;
    U370 : X_AND2 
      port map ( I0 => N305 , I1 => N18 , O => U370_2_INV ) ;
    U371 : X_OR2 
      port map ( I0 => I_0_N265(0) , I1 => N307 , O => I_0_N256 ) ;
    U372 : X_INV 
      port map ( I => N335 , O => N309 ) ;
    U373 : X_INV 
      port map ( I => N89 , O => N308 ) ;
    U375 : X_OR2 
      port map ( I0 => N309 , I1 => N139 , O => N310 ) ;
    U376 : X_AND2 
      port map ( I0 => N310 , I1 => N311 , O => U376_2_INV ) ;
    U377 : X_AND2 
      port map ( I0 => N19 , I1 => N18 , O => I_0_N265(0) ) ;
    U378 : X_INV 
      port map ( I => I_0_ECNT_E , O => N313 ) ;
    U379 : X_OR2 
      port map ( I0 => N317 , I1 => N313 , O => N314 ) ;
    U380 : X_AND2 
      port map ( I0 => N314 , I1 => I_0_CLREVENT273 , O => U380_2_INV ) ;
    U381 : X_INV 
      port map ( I => I_0_ECNT(4) , O => N315 ) ;
    U382 : X_OR2 
      port map ( I0 => N135 , I1 => N315 , O => N316 ) ;
    U384 : X_AND2 
      port map ( I0 => I_0_CLREVENT , I1 => N18 , O => U384_2_INV ) ;
    I_0_CLREVENT_REG : X_FF 
      port map ( I => I_0_CLREVENT273 , CLK => N17 , CE => I_0_N274 , 
      SET => GND , RST => I_0_CLREVENT_REG_GSR_OR , O => I_0_CLREVENT ) ;
    U385 : X_INV 
      port map ( I => N319 , O => N318 ) ;
    U388 : X_AND2 
      port map ( I0 => I_0_LT_114_LT_LT_AEQB(5) , 
      I1 => I_0_LT_114_LT_LT_AEQB(6) , O => N119 ) ;
    U389 : X_INV 
      port map ( I => N321 , O => N322 ) ;
    U390 : X_INV 
      port map ( I => N327 , O => N320 ) ;
    U391 : X_AND2 
      port map ( I0 => N320 , I1 => N18 , O => U391_2_INV ) ;
    U392 : X_OR2 
      port map ( I0 => I_1_N265(0) , I1 => N322 , O => I_1_N256 ) ;
    U393 : X_INV 
      port map ( I => N336 , O => N324 ) ;
    U394 : X_INV 
      port map ( I => N86 , O => N323 ) ;
    U396 : X_OR2 
      port map ( I0 => N324 , I1 => N140 , O => N325 ) ;
    U397 : X_AND2 
      port map ( I0 => N325 , I1 => N326 , O => U397_2_INV ) ;
    U398 : X_AND2 
      port map ( I0 => N18 , I1 => N20 , O => I_1_N265(0) ) ;
    U399 : X_INV 
      port map ( I => I_1_ECNT_E , O => N328 ) ;
    U400 : X_OR2 
      port map ( I0 => N332 , I1 => N328 , O => N329 ) ;
    U401 : X_AND2 
      port map ( I0 => N329 , I1 => I_1_CLREVENT273 , O => U401_2_INV ) ;
    U402 : X_INV 
      port map ( I => I_1_ECNT(4) , O => N330 ) ;
    U403 : X_OR2 
      port map ( I0 => N130 , I1 => N330 , O => N331 ) ;
    U405 : X_AND2 
      port map ( I0 => I_1_CLREVENT , I1 => N18 , O => U405_2_INV ) ;
    I_1_CLREVENT_REG : X_FF 
      port map ( I => I_1_CLREVENT273 , CLK => N17 , CE => I_1_N274 , 
      SET => GND , RST => I_1_CLREVENT_REG_GSR_OR , O => I_1_CLREVENT ) ;
    U406 : X_INV 
      port map ( I => N334 , O => N333 ) ;
    U409 : X_AND2 
      port map ( I0 => I_1_LT_114_LT_LT_AEQB(5) , 
      I1 => I_1_LT_114_LT_LT_AEQB(6) , O => N115 ) ;
    I_0_CLRZERO_REG_GSR_OR_0 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_0_CLRZERO_REG_GSR_OR ) ;
    I_0_EQ2_REG_GSR_OR_1 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_0_EQ2_REG_GSR_OR ) ;
    I_0_ST_INT_REG_GSR_OR_2 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_0_ST_INT_REG_GSR_OR ) ;
    I_0_ECNT_E_REG_GSR_OR_3 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_0_ECNT_E_REG_GSR_OR ) ;
    I_0_ECNT_REG_0_GSR_OR_4 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_0_ECNT_REG_0_GSR_OR ) ;
    I_1_ST_INT_REG_GSR_OR_5 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_1_ST_INT_REG_GSR_OR ) ;
    I_1_ECNT_E_REG_GSR_OR_6 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_1_ECNT_E_REG_GSR_OR ) ;
    I_0_ECNT_REG_2_GSR_OR_7 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_0_ECNT_REG_2_GSR_OR ) ;
    I_0_ECNT_REG_1_GSR_OR_8 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_0_ECNT_REG_1_GSR_OR ) ;
    I_0_ZCNT_REG_1_GSR_OR_9 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_0_ZCNT_REG_1_GSR_OR ) ;
    I_0_ZCNT_REG_0_GSR_OR_10 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_0_ZCNT_REG_0_GSR_OR ) ;
    I_0_ZCNT_REG_2_GSR_OR_11 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_0_ZCNT_REG_2_GSR_OR ) ;
    I_1_ECNT_REG_1_GSR_OR_12 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_1_ECNT_REG_1_GSR_OR ) ;
    I_1_ECNT_REG_0_GSR_OR_13 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_1_ECNT_REG_0_GSR_OR ) ;
    I_1_ECNT_REG_2_GSR_OR_14 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_1_ECNT_REG_2_GSR_OR ) ;
    I_1_ZCNT_REG_2_GSR_OR_15 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_1_ZCNT_REG_2_GSR_OR ) ;
    I_1_ZCNT_REG_1_GSR_OR_16 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_1_ZCNT_REG_1_GSR_OR ) ;
    I_1_ZCNT_REG_0_GSR_OR_17 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_1_ZCNT_REG_0_GSR_OR ) ;
    I_1_CLRZERO_REG_GSR_OR_18 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_1_CLRZERO_REG_GSR_OR ) ;
    I_0_E2RQ_REG_GSR_OR_19 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_0_E2RQ_REG_GSR_OR ) ;
    I_1_E2RQ_REG_GSR_OR_20 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_1_E2RQ_REG_GSR_OR ) ;
    I_0_ECNT_REG_4_GSR_OR_21 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_0_ECNT_REG_4_GSR_OR ) ;
    I_0_DCNT_REG_2_GSR_OR_22 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_0_DCNT_REG_2_GSR_OR ) ;
    I_0_DCNT_REG_0_GSR_OR_23 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_0_DCNT_REG_0_GSR_OR ) ;
    I_0_ZCNT_REG_6_GSR_OR_24 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_0_ZCNT_REG_6_GSR_OR ) ;
    I_0_ZCNT_REG_4_GSR_OR_25 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_0_ZCNT_REG_4_GSR_OR ) ;
    I_1_EQ2_REG_GSR_OR_26 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_1_EQ2_REG_GSR_OR ) ;
    I_1_ECNT_REG_4_GSR_OR_27 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_1_ECNT_REG_4_GSR_OR ) ;
    I_1_ZCNT_REG_6_GSR_OR_28 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_1_ZCNT_REG_6_GSR_OR ) ;
    I_1_ZCNT_REG_4_GSR_OR_29 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_1_ZCNT_REG_4_GSR_OR ) ;
    I_1_DCNT_REG_2_GSR_OR_30 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_1_DCNT_REG_2_GSR_OR ) ;
    I_1_DCNT_REG_0_GSR_OR_31 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_1_DCNT_REG_0_GSR_OR ) ;
    I_0_ZCNT_E_REG_GSR_OR_32 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_0_ZCNT_E_REG_GSR_OR ) ;
    I_1_ZCNT_E_REG_GSR_OR_33 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_1_ZCNT_E_REG_GSR_OR ) ;
    I_0_ECNT_REG_3_GSR_OR_34 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_0_ECNT_REG_3_GSR_OR ) ;
    I_0_DCNT_REG_1_GSR_OR_35 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_0_DCNT_REG_1_GSR_OR ) ;
    I_0_ZCNT_REG_3_GSR_OR_36 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_0_ZCNT_REG_3_GSR_OR ) ;
    I_0_ZCNT_REG_5_GSR_OR_37 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_0_ZCNT_REG_5_GSR_OR ) ;
    I_1_ECNT_REG_3_GSR_OR_38 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_1_ECNT_REG_3_GSR_OR ) ;
    I_1_ZCNT_REG_3_GSR_OR_39 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_1_ZCNT_REG_3_GSR_OR ) ;
    I_1_ZCNT_REG_5_GSR_OR_40 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_1_ZCNT_REG_5_GSR_OR ) ;
    I_1_DCNT_REG_1_GSR_OR_41 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_1_DCNT_REG_1_GSR_OR ) ;
    I_0_CLREVENT_REG_GSR_OR_42 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_0_CLREVENT_REG_GSR_OR ) ;
    I_1_CLREVENT_REG_GSR_OR_43 : X_OR2 
      port map ( I0 => I_0_N1163 , I1 => GSR , O => I_1_CLREVENT_REG_GSR_OR ) ;
    U163_1I20 : X_BUF 
      port map ( I => N335 , O => U163_1I20_GTS_TRI ) ;
    U163_1I20_GTS_TRI_44 : X_TRI 
      port map ( I => U163_1I20_GTS_TRI , O => ST_A , 
      CTL => U163_1I20_GTS_TRI_2_INV ) ;
    U164_1I20 : X_BUF 
      port map ( I => N336 , O => U164_1I20_GTS_TRI ) ;
    U164_1I20_GTS_TRI_45 : X_TRI 
      port map ( I => U164_1I20_GTS_TRI , O => ST_B , 
      CTL => U164_1I20_GTS_TRI_2_INV ) ;
    U159_CLKBUF : X_CKBUF 
      port map ( I => U159_CLKIO_BUFSIG , O => N17 ) ;
    U159_CLKIO_BUF : X_BUF 
      port map ( I => CLOCK , O => U159_CLKIO_BUFSIG ) ;
    U170_N153_2_0 : X_AND2 
      port map ( I0 => I_1_N265(0) , I1 => N152 , O => U170_2_0 ) ;
    U170_N153 : X_AND2 
      port map ( I0 => U170_2_0 , I1 => I_1_EQ2 , O => U170_N153_2_INV ) ;
    U173_I_1_N301_2_0 : X_AND2 
      port map ( I0 => N336 , I1 => N155 , O => U173_2_0 ) ;
    U173_I_1_N301 : X_AND2 
      port map ( I0 => U173_2_0 , I1 => N18 , O => I_1_N301 ) ;
    U175_N157_2_0 : X_AND2 
      port map ( I0 => I_0_N265(0) , I1 => N156 , O => U175_2_0 ) ;
    U175_N157 : X_AND2 
      port map ( I0 => U175_2_0 , I1 => N335 , O => U175_N157_2_INV ) ;
    U177_N158_2_0 : X_OR2 
      port map ( I0 => I_0_ZCNT(3) , I1 => I_0_LT_114_LT_LT_AEQB(2) , 
      O => U177_2_0 ) ;
    U177_N158 : X_OR2 
      port map ( I0 => U177_2_0 , I1 => I_0_ZCNT(4) , O => N158 ) ;
    U181_N160_2_0 : X_AND2 
      port map ( I0 => I_0_N265(0) , I1 => N159 , O => U181_2_0 ) ;
    U181_N160 : X_AND2 
      port map ( I0 => U181_2_0 , I1 => I_0_EQ2 , O => U181_N160_2_INV ) ;
    U184_I_0_N301_2_0 : X_AND2 
      port map ( I0 => N335 , I1 => N162 , O => U184_2_0 ) ;
    U184_I_0_N301 : X_AND2 
      port map ( I0 => U184_2_0 , I1 => N18 , O => I_0_N301 ) ;
    U185_N122_2_0 : X_OR2 
      port map ( I0 => I_0_ECNT(4) , I1 => I_0_ECNT(3) , O => U185_2_0 ) ;
    U185_N122_2_1 : X_OR2 
      port map ( I0 => I_0_ECNT(2) , I1 => I_0_ECNT(1) , O => U185_2_1 ) ;
    U185_N122 : X_OR2 
      port map ( I0 => U185_2_0 , I1 => U185_2_1 , O => U185_N122_2_INV ) ;
    U186_N118_2_0 : X_OR2 
      port map ( I0 => I_1_ECNT(4) , I1 => I_1_ECNT(3) , O => U186_2_0 ) ;
    U186_N118_2_1 : X_OR2 
      port map ( I0 => I_1_ECNT(2) , I1 => I_1_ECNT(1) , O => U186_2_1 ) ;
    U186_N118 : X_OR2 
      port map ( I0 => U186_2_0 , I1 => U186_2_1 , O => U186_N118_2_INV ) ;
    U189_N102_2_0 : X_OR2 
      port map ( I0 => N164 , I1 => N163 , O => U189_2_0 ) ;
    U189_N102_2_1 : X_OR2 
      port map ( I0 => N120 , I1 => N139 , O => U189_2_1 ) ;
    U189_N102 : X_OR2 
      port map ( I0 => U189_2_0 , I1 => U189_2_1 , O => U189_N102_2_INV ) ;
    U192_N101_2_0 : X_OR2 
      port map ( I0 => N166 , I1 => N165 , O => U192_2_0 ) ;
    U192_N101_2_1 : X_OR2 
      port map ( I0 => N335 , I1 => I_0_EQ2 , O => U192_2_1 ) ;
    U192_N101 : X_OR2 
      port map ( I0 => U192_2_0 , I1 => U192_2_1 , O => U192_N101_2_INV ) ;
    U194_N103_2_0 : X_AND2 
      port map ( I0 => I_1_ECNT(1) , I1 => N167 , O => U194_2_0 ) ;
    U194_N103_2_1 : X_AND2 
      port map ( I0 => I_1_E2RQ , I1 => N18 , O => U194_2_1 ) ;
    U194_N103 : X_AND2 
      port map ( I0 => U194_2_0 , I1 => U194_2_1 , O => U194_N103_2_INV ) ;
    U195_N130_2_0 : X_OR2 
      port map ( I0 => I_1_ECNT(3) , I1 => I_1_ECNT(2) , O => U195_2_0 ) ;
    U195_N130_2_1 : X_OR2 
      port map ( I0 => I_1_ECNT(1) , I1 => I_1_ECNT(0) , O => U195_2_1 ) ;
    U195_N130 : X_OR2 
      port map ( I0 => U195_2_0 , I1 => U195_2_1 , O => N130 ) ;
    U197_N104_2_0 : X_AND2 
      port map ( I0 => I_0_ECNT(1) , I1 => N168 , O => U197_2_0 ) ;
    U197_N104_2_1 : X_AND2 
      port map ( I0 => N18 , I1 => I_0_E2RQ , O => U197_2_1 ) ;
    U197_N104 : X_AND2 
      port map ( I0 => U197_2_0 , I1 => U197_2_1 , O => U197_N104_2_INV ) ;
    U198_N135_2_0 : X_OR2 
      port map ( I0 => I_0_ECNT(3) , I1 => I_0_ECNT(2) , O => U198_2_0 ) ;
    U198_N135_2_1 : X_OR2 
      port map ( I0 => I_0_ECNT(1) , I1 => I_0_ECNT(0) , O => U198_2_1 ) ;
    U198_N135 : X_OR2 
      port map ( I0 => U198_2_0 , I1 => U198_2_1 , O => N135 ) ;
    U214_N182_2_0 : X_OR2 
      port map ( I0 => N181 , I1 => I_0_ZCNT(0) , O => U214_2_0 ) ;
    U214_N182 : X_OR2 
      port map ( I0 => U214_2_0 , I1 => I_0_CLRZERO , O => U214_N182_2_INV ) ;
    U235_N205_2_0 : X_OR2 
      port map ( I0 => N202 , I1 => I_1_ZCNT(0) , O => U235_2_0 ) ;
    U235_N205 : X_OR2 
      port map ( I0 => U235_2_0 , I1 => I_1_CLRZERO , O => U235_N205_2_INV ) ;
    U238_N109_2_0 : X_OR2 
      port map ( I0 => N204 , I1 => N203 , O => U238_2_0 ) ;
    U238_N109_2_1 : X_OR2 
      port map ( I0 => N116 , I1 => N140 , O => U238_2_1 ) ;
    U238_N109 : X_OR2 
      port map ( I0 => U238_2_0 , I1 => U238_2_1 , O => U238_N109_2_INV ) ;
    U241_N108_2_0 : X_OR2 
      port map ( I0 => N207 , I1 => N206 , O => U241_2_0 ) ;
    U241_N108_2_1 : X_OR2 
      port map ( I0 => I_1_EQ2 , I1 => N336 , O => U241_2_1 ) ;
    U241_N108 : X_OR2 
      port map ( I0 => U241_2_0 , I1 => U241_2_1 , O => U241_N108_2_INV ) ;
    U262_N223_2_0 : X_AND2 
      port map ( I0 => I_1_N265(0) , I1 => N222 , O => U262_2_0 ) ;
    U262_N223 : X_AND2